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rx63t group renesas mcus r01ds0087ej0220 rev.2.20 page 1 of 186 mar 31, 2016 datasheet features 32-bit rx cpu core ? max. operating frequency: 100 mhz capable of 165 dmips in operation at 100 mhz ? single precision 32-bit ieee-754 floating point ? two types of multiply-and-accumula tion unit (between memories and between registers) ? 32-bit multiplier (fastest instruction execution takes one cpu clock cycle) ? divider (fastest instruction execution takes two cpu clock cycles) ? fast interrupt ? cisc harvard architecture with 5-stage pipeline ? variable-length instructions: ultra-compact code ? supports the memory protection unit (mpu) ? two types of debugging interfaces: jtag and fine (two-line) low-power design and architecture ? single 3.3-v supply or single 5-v supply; 3.3-v products can be used with a 5-v analog power supply ? four low-power modes on-chip main flash memory, no wait states ? 100-mhz operation, 10-ns read cycle (no wait states) ? max. 512 kbytes ? user code is programmable by usb, sci, or jtag. on-chip data flash memory ? max. 32 kbytes, reprogrammable up to 100,000 times ? programming/erasing as background operations (bgos) on-chip sram, no wait states ? max. 48 kbytes ? for instructions and operands dma ? dma: incorporates four channels ? dtc: a single unit can handle transfer on multiple channels. reset and supply management ? power-on reset (por) ? low voltage detection (lvd) with voltage settings clock functions ? external crystal oscillator or internal pll for operation at 4 to 12.5 mhz ? internal 125-khz loco ? dedicated 125-khz loco for the iwdt independent watchdog timer ? 125-khz loco clock operation useful functions for iec60730 compliance ? oscillation-stop detection, frequ ency measurement, crc, iwdt, self-diagnostic function for the a/d converter, etc. external address space ? 4 cs areas (4 1 mbyte) ? multiplexed address data or separate address lines are selectable per area. ? 8- or 16-bit bus space is selectable per area. up to 11 communications interfaces ? usb 2.0 full-speed function interface (1 channel) ? can (compliant with iso11898-1), incorporating 32 mailboxes (1 channel) ? sci with multiple functionalities (5 channels) choose from among asynchronous mode, clock-synchronous mode, smart-card interface mode, simple spi, simple i 2 c, and extended serial mode. ? i 2 c bus interface for smbus (2 channels) ? rspi for high-speed transfer (2 channels) up to twenty 16-bit timers ? 16-bit mtu3: 100-mhz operation, input capture, output compare, three-phase complementary pwm wa veform output (2 channels), phase-counting mode (8 channels); complementary pwm does not burden the cpu. ? 16-bit gpt: 100-mhz operation, input capture, output compare, 4- channel single-phase complementary pwm waveform output or 1- channel three-phase complementary + 1-channel single-phase complementary output, interlocking with comparator (counter operation, pwm negation control), detection of abnormal oscillation frequencies (useful for iec60730 compliance) (8 channels); complementary pwm does not burden the cpu. ? 16-bit cmt (4 channels) generation of delays in pwm waveforms (for products with the product id code 1) ? the timing with which signals on the 16-bit gpt pwm output pin rise and fall can be controlled with an accuracy of up to 312 ps (in operation at 100 mhz). two a/d converters for 1-mhz operation, total of 8 channels ? simultaneous sampling on 7 channels is possible with three units. ? self-diagnosis function (use ful for iec60730 compliance) ? two 12-bit adcs: three sample-and-hold circuits, double data registers, amplifier, comparator (8 channels) ? one 10-bit adc (12 channels) one a/d converter for 2-mhz operation, total of 20 channels ? one 10-bit adc (20 channels) 10-bit d/a converter: 2 channels digital power supply controller-dedicated calculation function (for products with product id code 1) ? 16-bit fixed-point calculation func tion that handles compensatory calculations in the method of di gital control for switched-mode power supplies. register write protection function can protect values in important registers against overwriting. up to 110 pins for gpio ? open drain, switchable driving ability operating temp. range ? ?40 ? c to +85 ? c ? ?40 ? c to +105 ? c plqp0144ka-a 20 20mm, 0.5mm pitch plqp0120ka-a 16 16mm, 0.5mm pitch plqp0112ja-a 20 20mm, 0.65mm pitch plqp0100kb-a 14 14mm, 0.5mm pitch plqp0064kb-a 10 10mm, 0.5mm pitch PLQP0048KB-A 7 7mm, 0.5mm pitch 100-mhz 32-bit rx mcu, on-chip fpu, 165 dmips, two 12-bit adcs (three s/h circuits, double data registers, amplifier, comparator), one 10-bit adc, simultaneous sampling on 7 channels using three adcs, 100 mhz pwm (2 three-phase complementary channels + 4 single-phase complementary channels or 3 three-phase complementary channels + 1 single-phase complementary channel) r01ds0087ej0220 rev.2.20 mar 31, 2016 features
r01ds0087ej0220 rev.2.20 page 2 of 186 mar 31, 2016 rx63t group 1. overview 1. overview 1.1 outline of specifications table 1.1 lists the specifications in outline, and table 1.2 lists the functions of products. table 1.1 shows an outline of the maximum specifications, and the available peripheral modules and number of channels differ according to the number of pins on the package and the rom capacity. for details, see table 1.2, comparison of functions for different packages . table 1.1 outline of specifications (1/7) classification module/function description cpu cpu ? maximum operating frequency: 100 mhz ? 32-bit rx cpu ? minimum instruction execution time: one inst ruction per state (cycle of the system clock) ? address space: 4-gbyte linear ? register set of the cpu general purpose: sixteen 32-bit registers control: nine 32-bit registers accumulator: one 64-bit register ? basic instructions: 73 ? floating-point operation instructions: 8 ? dsp instructions: 9 ? addressing modes: 10 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32 32 ? 64 bits ? on-chip divider: 32 / 32 ? 32 bits ? barrel shifter: 32 bits ? memory protection unit (mpu) fpu ? single precision float ing point (32 bits) ? data types and floating-point exceptions in conformance with the ieee754 standard memory rom ? capacity: 512 kbytes, 384 kbytes, 256 kbytes, 64 kbytes, 48 kbytes, 32 kbytes ? 100 mhz, no-wait access ? on-board programming: programs can be modified through sci or usb while the mcu is mounted on the board. ? off-board programming: programs can be modified using parallel programmer. (only in 144-, 120-, 112- and 100-pin versions) ram ? capacity: 48 kbytes, 32 kbytes, 24 kbytes, 8 kbytes ? 100 mhz, no-wait access e 2 data flash ? capacity: 32 kbytes, 8 kbytes ? programming/erasing: 100,000 times ? on-board programming: programs can be modified through sci or usb while the mcu is mounted on the board. programming from the user program is possible. mcu operating modes [144-, 120-, 112- and 100-pin versions] single-chip mode, on-chip rom enabled extended mode, on-chip rom disabled extended mode (switchable by software) [64- and 48-pin versions] single-chip mode
r01ds0087ej0220 rev.2.20 page 3 of 186 mar 31, 2016 rx63t group 1. overview clock clock generation circuit ? main clock oscillator, low-speed on-chip oscillator, pll freq uency synthesizer, and dedicated on-chip oscillator for the iwdt ? main-clock oscillation stop detection ? separate frequency-division and multiplication settings for the system clock (iclk), peripheral module clock (pclka), peri pheral module clock (pclkb), ad clock (pclkc), flashif clock (fclk) and s12ad clock (pclkd). the cpu and other bus masters run in sync hronization with the system clock (iclk): up to 100 mhz multi-function timer pulse unit 3 and general pwm timer run in synchronization with pclka: up to 100 mhz peripheral modules run in synchronization wi th the peripheral module clock (pclkb): up to 50 mhz flash if run in synchronization with the flashif clock (fclk): up to 50 mhz devices connected to the external bus run in synchronization with the external bus clock (bclk): up to 50 mhz 10-bit a/d converter runs in synchronization with the ad clock (pclkc): up to 100 mhz 12-bit a/d converter runs in synchronizati on with the s12ad clock (pclkd): up to 50 mhz clock clock frequency accuracy measurement circuit (cac) the frequency of the following clocks can be measured; the main clock oscillator, pll circuit, and iwdt-dedicated on-chip oscillator. reset res# pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer reset, watchdog timer reset, deep software standby reset, and software reset voltage detection circuit when the voltage on vcc passes the voltage detection level (vdet), an internal reset or internal interrupt is generated. low power consumption low power consumption facilities ? module stop function ? four low power consumption modes sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode interrupt interrupt controller (icub) ? peripheral function interrupts: up to 169 sources ? external interrupts: up to 8 (pins irq0 to irq7) ? software interrupts: one source ? non-maskable interrupts: 6 sources ? sixteen levels specifiable for the order of priority external bus extension ? the external address space can be divided into four areas (cs0 to cs3), each with independent control of access settings. capacity of each area: 1 mbyte (cs0 to cs3) a chip-select signal (cs0# to cs3#) can be output for each area. each area is specifiable as an 8- or 16-bit bus space the data arrangement in each area is select able as little or big endian (only for data). ? bus format: separate bus, multiplex bus ? wait control ? write buffer facility dma dma controller (dmaca) ? 4 channels ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: software trigger, exter nal interrupts, and interrupt requests from peripheral functions data transfer controller (dtca) ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: software interrupt activa tion register settings, external interrupts, and interrupt requests from peripheral functions table 1.1 outline of specifications (2/7) classification module/function description
r01ds0087ej0220 rev.2.20 page 4 of 186 mar 31, 2016 rx63t group 1. overview i/o ports general i/o ports ? 144-pin lqfp i/o pins: 81 input pins: 29 open-drain outputs: 27 ? 120-pin lqfp i/o pins: 72 input pin: 21 open-drain outputs: 26 ? 112-pin lqfp i/o pins: 69 input pins: 21 open-drain outputs: 20 ? 100-pin lqfp i/o pins: 57 input pins: 21 open-drain outputs: 16 ? 64-pin lqfp i/o pins: 39 input pins: 9 open-drain outputs: 10 5-v tolerance: 39 ? 48-pin lqfp i/o pins: 25 input pins: 7 open-drain outputs: 8 5-v tolerance: 25 timers multi-function timer pulse unit 3 (mtu3) ? (16 bits 8 channels) ? maximum of 16 pulse-input/out put and 3 pulse-input possible ? select eight clocks from among ten count clocks (pclka/1, pclka/4, pclka/16, pclka/64, pclka/256, pclka/1024, mtclka, mtclkb, mtclkc, and mtclkd) for each channel (seven clocks for channel 1, four clo cks for channel 5, and six clocks for channel 6 or 7) ? 24 output compare/input capture registers ? counter-clearing operation (simultaneous cl earing on compare match or input capture) ? simultaneous writing to multiple timer counters (tcnt) ? simultaneous input and output to registers in synchronization with counter operations ? buffer operation specifiable ? capable of cascade-connected operation ? interrupts: 38 sources ? automatic transfer of register data ? pulse output modes topple, pwm, complementary pwm, and reset-synchronous pwm modes ? complementary pwm output mode outputs non-overlapping waveforms for controlling 3-phase inverters automatic specification of dead times pwm duty cycle: selectable as any value from 0% to 100% delay can be applied to requests for a/d conversion. non-generation of interrupt requests at peak or trough values of counters can be selected. double buffering ? reset-synchronous pwm mode three pwm waveforms and corresponding inverse waveforms are output with the desired duty cycles. ? phase-counting mode ? counter functionality for dead-time compensation ? generation of triggers for a/d converters ? differential timing for initiation of a/d conversion port output enable 3 (poe3) ? control of the high-impedance state of the mtu3 and gpt?s waveform output pins ? six pins for input from signal sources: poe0, poe4, poe8, poe10, poe11, and poe12 ? initiation on detection of short-circui ted outputs (detection of pwm outputs having simultaneously become an active level.) ? initiation by comparator-detection, os cillation-stoppage detection, or software ? software control of the states of pi ns for output control can also be added. table 1.1 outline of specifications (3/7) classification module/function description
r01ds0087ej0220 rev.2.20 page 5 of 186 mar 31, 2016 rx63t group 1. overview timers general pwm timer (gpt) ? 16 bits x 8 channels ? counting up or down (saw-wave), counting up and down (triangle-wave) selectable for all channels ? select from among four count clocks (pclka/1, pclka/4, pclka/8, and pclka/16) for each channel ? 2 input/output pins per channel ? 2 output compare/input capture registers per channel ? for the 2 output compare/input capture r egisters of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use. ? in output compare operation, buffer switching can be at peaks or troughs, enabling the generation of laterally asymmetrically pwm waveforms. ? registers for setting up frame intervals on each channel (with capability for generating interrupts on overflow or underflow) ? synchronizable operation of the several counters ? modes of synchronized operation (synchroni zed, or displaced by desired times for phase shifting) ? generation of dead times in pwm operation ? through combination of three counters, generation of automatic three-phase pwm waveforms incorporating dead times ? starting, clearing, and stopping counters in re sponse to external or internal triggers ? internal trigger sources: output of the in ternal comparator detection, software, and compare-match ? the main clock can be used as a counter cloc k for measuring the timing of the edges of signals produced by frequency-dividing the dedi cated clock signal for the iwdt (to detect abnormal oscillation). ? a pwm delay with an accuracy of up to 1/32 times the period of the system clock (iclk) can be generated to control the timing with which signals from the two pwm output pins from each of channels 0 to 3 rise and fall. compare match timer (cmt) ? (16 bits 2 channels) 2 units ? select from among four internal clock si gnals (pclk/8, pclk/32, pclk/128, pclk/ 512) watchdog timer (wdta) ? 14 bits 1 channel ? select from among 6 counter-input clock si gnals (pclk/4, pclk/64, pclk/128, pclk/ 512, pclk/2048, pclk/8192) independent watchdog timer (iwdta) ? 14 bits 1 channel ? counter-input clock: dedicated on-chip oscillator ? dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated clock/128, dedicated clock/256 communication function usb 2.0 host/function module (usba) ? includes a udc (usb device controller) and transceiver for usb 2.0 ? single port ? compliance with the usb 2.0 specification ? transfer rate: full speed (12 mbps) ? self-power mode and bus power mode are selectable ? supports the otg (on-the-go) ? incor porates 2 kbytes of ram as a transfer buffer serial communications interfaces (scic, scid) ? 5 channels (scic: 4 channels + scid: 1 channel) ? scic serial communications modes: asynchronou s, clock synchronous, and smart-card interface multi-processor function on-chip baud rate generator allows selection of the desired bit rate choice of lsb-first or msb-first transfer simple i 2 c simple spi ? scid (the following functions are added to scic) supports the serial communications protoc ol, which contains the start frame and information frame supports the lin format table 1.1 outline of specifications (4/7) classification module/function description
r01ds0087ej0220 rev.2.20 page 6 of 186 mar 31, 2016 rx63t group 1. overview communication function i 2 c bus interfaces (riic) ? 2 channels communication formats i 2 c bus format/smbus format supports the multi-master max. transfer rate: 400 kbps can module (can) ? 1 channels ? compliance with the iso11898-1 specific ation (standard frame and extended frame) ? 32 mailboxes per channel serial peripheral interfaces (rspi) ? 2 channels ? rspi transfer facility using the mosi (master out, slave in), miso (master in, slave out), ssl (slave select), and rspck (rspi clock) signals enables se rial transfer through spi operation (four lines) or clock-synchr onous operation (three lines) capable of handling serial transfer as a master or slave ? data formats switching between msb first and lsb first the number of bits in each transfer can be changed to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) ? buffered structure double buffers for both transmission and reception ? max. transfer rate in master mode: [144-, 120-, 112- and 100-pin versions] 25 mbps [64- and 48-pin versions] 12.5 mbps in slave mode: 6.25 mbps 12-bit a/d converter (s12adb) [144-, 120-, 112- and 100-pin versions] ? 12 bits (4 channels x 2 unit) ? 12-bit resolution ? conversion time 1.0 ? s per channel (clock for s12adb, pclk d (a/d conversion clock adclk) = 50 mhz, avcc0 = 4.0 to 5.5 v) 2.0 ? s per channel (clock for s12adb, pclk d (a/d conversion clock adclk) = 25 mhz, avcc0 = 3.0 to 3.6 v) ? operating modes scan mode (single-cycle scan mode/ continuous scan mode/group scan mode) group a priority control (only for the group scan mode) ? sample-and-hold function a common sample-and-hold circ uit for units is included. additionally, sample-and-hold circuit for eac h unit is included. (three channels per unit) ? self-diagnostic function the self-diagnostic function internally gener ates three analog input voltages (vrefl0, vrefh0 x 1/2, vrefh0). ? double trigger mode (duplicat ion of a/d converted data) ? input signal amplification function using programmable gai n amplifier (three channels per unit) amplification factors: 2.0 times, 2.5 times, 3.077 times, 3.636 times, 4.0 times, 4.444 times, 5.0 times, 5.714 times, 6.667 times, 10.0 times, 13.333 times (total of 11 steps) ? three ways to start a/d conversion conversion can be started by software, a conv ersion start trigger from a timer (mtu3 or gpt), or an external trigger signal. ? window comparators (three channels per unit) table 1.1 outline of specifications (5/7) classification module/function description
r01ds0087ej0220 rev.2.20 page 7 of 186 mar 31, 2016 rx63t group 1. overview 12-bit a/d converter (s12adb) [64- and 48-pin versions] ? 12 bits (8 channels x 1 unit) ? 12-bit resolution ? conversion time 1.0 s per channel (s12adb clock: pclkd (a/d conversion clock: adclk) = 50 mhz ? operating modes scan mode (single scan mode / continuous scan mode / group scan mode) group a priority control (group scan mode only) ? sample-and-hold function a common sample-and-hold circ uit for units is included separate sample-and-hold circuits are also included (three channels per unit) ? self-diagnosis function three analog input voltages (vrefl0, vrefh0 1/2, vrefh0) can be generated internally by the self-diagnosis function. ? double trigger mode (double the results of a/d conversion) ? three ways to start a/d conversion conversion can be started by software, a conv ersion start trigger from a timer (mtu3 or gpt), or an external trigger signal. ? window comparators (three channels per unit) 10-bit a/d converter (ada) 10 bits (20 channels 1 unit) ? 10-bit resolution ? conversion time 0.5 s per channel (a/d conv ersion clock adclk = 100 mhz) ? two operating modes single mode, scan mode ? scan mode single-cycle scan mode continuous scan mode ? sample-and-hold function a common sample-and-hold circ uit for units is included ? three ways to start a/d conversion conversion can be started by software, a conv ersion start trigger from a timer (mtu3 or gpt), or an external trigger signal. ? 8-bit precision output 2-bit right shifting for output of conversion results is selectable. ? self-diagnostic function the self-diagnostic function internally generates three analog input voltages (avss, vref x 1/2, vref) d/a converter (daa) ? 2 channels ? 10-bit resolution ? output voltage: 0 v to vref crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-bit units ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1. ? generation of crc codes for use with lsb- first or msb-first communications is selectable data operating circuit (doc) ? comparison, addition, and subtraction of 16-bit data digital power supply controller (dpc) ? control parameters calculation unit of t he digital switch-mode power supply systems. ? adopt robust control algorithm with high control stability ? results of measurement by the 10-bit a/d converter can be used in calculating the control parameters. operating frequency up to 100 mhz power supply voltage [144-, 120-, 112- and 100-pin versions] ? 3-v product vcc = pllvcc = vcc_usb = 2.7 to 3.6 v avcc0 = avcc = vref = 3.0 to 3.6 v, or 4.0 to 5.5 v vrefh0 = 3.0 to avcc0, or 4.0 to avcc0 ? 5-v product vcc = pllvcc = 4.0 to 5.5 v vcc_usb = 3.0 to 3.6 v avcc0 = avcc = vref = 4.0 to 5.5 v vrefh0 = 4.0 to avcc0 power supply voltage [64- and 48-pin versions] vcc = 2.7 to 3.6 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 table 1.1 outline of specifications (6/7) classification module/function description
r01ds0087ej0220 rev.2.20 page 8 of 186 mar 31, 2016 rx63t group 1. overview note 1. please contact renesas electronics sales office for derat ing of operation under ta = +85c to +105c. derating is the systematic reduction of load for th e sake of improved reliability. operating temperature d version: -40 to +85c, g version: -40 to +105c * 1 package 144-pin lqfp (plqp0144ka-a (20 20, 0.5-mm pitch)) 120-pin lqfp (plqp0120ka-a (16 16, 0.5-mm pitch)) 112-pin lqfp (plqp0112ja-a (20 20, 0.65-mm pitch)) 100-pin lqfp (plqp0100kb-a (14 14, 0.5-mm pitch)) 64-pin lqfp (plqp0064kb-a (10 10, 0.5-mm pitch)) 48-pin lqfp (PLQP0048KB-A (07 07, 0.5-mm pitch)) on-chip debugging system ? e1 emulator (jtag and fine interfaces) ? e20 emulator (jtag interface) table 1.1 outline of specifications (7/7) classification module/function description
r01ds0087ej0220 rev.2.20 page 9 of 186 mar 31, 2016 rx63t group 1. overview note 1. for the mtu3 and gpt, the number of pins will differ with the package. see the list of pins and pin functions for detail s. in addition, the can module is an optional function. for details, see table 1.3. note 2. not provided for the product id code o. table 1.2 comparison of functions for different packages functions rx63t group package 144 pins 120 pins 112 pins 100 pins 64 pins 48 pins external bus 16 bits ? external address space 1 mbyte 4 areas ? dma dma controller (dmaca) ch. 0 to 3 data transfer controller (dtca) supported interrupt controller (icub) nmi pin supported irq pin supported (x 8) supported (x 6) timers multi-function timer pulse unit 3 (mtu3)* 1 ch. 0 to 7 general pwm timer (gpt)* 1 generation of delays in pwm, not supported ch. 0 to 7 ch. 0 to 3 generation of delays in pwm, supported ch. 0 to 3 ? port output enable 3 (poe3) supported (poe pins 6) supported (poe pins 5) supported (poe pins 4) compare match timer (cmt) ch. 0 to 3 watchdog timer (wdta) supported independent watchdog timer (iwdta) supported communication function usb2.0 host/function module (usba) ch. 0 ? serial communications interfaces (sclc) ch. 0 to 3 ch. 0 to 2 ch. 0, 1 serial communications interfaces (scld) ch. 12 i 2 c bus interfaces (riic) ch. 0, 1 ch. 0 serial peripheral interfaces (rspi) ch. 0, 1 ch. 0 can module (can) (as an optional function)* 1 ch. 0 ? 12-bit a/d converter (s12adb) 4 channels 2 units 8 channels 1 unit (an000 to 007) 8 channels 1 unit (an000 to 004, 007) three-channel simultaneous sampling function 2 units 1 unit programmable gain amplifier 3 channels 2 units ? window comparator 3 channels 2 units 3 channels 1 unit 10-bit a/d converter (ada) 20 channels 12 channels ? d/a converter (daa) ch. 0, 1 ? clock frequency accuracy measurement circuit supported digital power supply controller (dpc)* 2 supported not supported
r01ds0087ej0220 rev.2.20 page 10 of 186 mar 31, 2016 rx63t group 1. overview 1.2 list of products table 1.3 is a list of products, and figure 1.1 shows how to read the product part number. table 1.3 list of products (1/4) group part no. order part no. package on-chip rom capacity on-chip ram capacity option operating voltage operating temperature rx63t r5f563teadfb r5f563teadfb#v0 plqp0144ka-a 512 kbytes 48 kbytes can module included vcc/ pllvcc 4.0 to 5.5v vcc_usb 3.0 to 3.6v avcc/ avcc0 4.0 to 5.5v -40 to +85c (d version) r5f563teadfb r5f563teadfb#v1 plqp0144ka-a 512 kbytes 48 kbytes can module included r5f563teadfa r5f563teadfa#v0 plqp0120ka-a 512 kbytes 48 kbytes can module included r5f563teadfa r5f563teadfa#v1 plqp0120ka-a 512 kbytes 48 kbytes can module included r5f563teadfh r5f563teadfh#v0 plqp0112ja-a 512 kbytes 48 kbytes can module included r5f563teadfh r5f563teadfh#v1 plqp0112ja-a 512 kbytes 48 kbytes can module included r5f563teadfp r5f563teadfp#v0 plqp0100kb-a 512 kbytes 48 kbytes can module included r5f563teadfp r5f563teadfp#v1 plqp0100kb-a 512 kbytes 48 kbytes can module included r5f563tcadfb r5f563tcadfb#v0 plqp0144ka-a 384 kbytes 32 kbytes can module included r5f563tcadfb r5f563tcadfb#v1 plqp0144ka-a 384 kbytes 32 kbytes can module included r5f563tcadfa r5f563tcadfa#v0 plqp0120ka-a 384 kbytes 32 kbytes can module included r5f563tcadfa r5f563tcadfa#v1 plqp0120ka-a 384 kbytes 32 kbytes can module included r5f563tcadfh r5f563tcadfh#v0 plqp0112ja-a 384 kbytes 32 kbytes can module included r5f563tcadfh r5f563tcadfh#v1 plqp0112ja-a 384 kbytes 32 kbytes can module included r5f563tcadfp r5f563tcadfp#v0 plqp0100kb-a 384 kbytes 32 kbytes can module included r5f563tcadfp r5f563tcadfp#v1 plqp0100kb-a 384 kbytes 32 kbytes can module included r5f563tbadfb r5f563tbadfb#v0 plqp0144ka-a 256 kbytes 24 kbytes can module included r5f563tbadfb r5f563tbadfb#v1 plqp0144ka-a 256 kbytes 24 kbytes can module included r5f563tbadfa r5f563tbadfa#v0 plqp0120ka-a 256 kbytes 24 kbytes can module included r5f563tbadfa r5f563tbadfa#v1 plqp0120ka-a 256 kbytes 24 kbytes can module included r5f563tbadfh r5f563tbadfh#v0 plqp0112ja-a 256 kbytes 24 kbytes can module included r5f563tbadfh r5f563tbadfh#v1 plqp0112ja-a 256 kbytes 24 kbytes can module included r5f563tbadfp r5f563tbadfp#v0 plqp0100kb-a 256 kbytes 24 kbytes can module included r5f563tbadfp r5f563tbadfp#v1 plqp0100kb-a 256 kbytes 24 kbytes can module included r5f563teddfb r5f563teddfb#v0 plqp0144ka-a 512 kbytes 48 kbytes can module not included r5f563teddfa r5f563teddfa#v0 plqp0120ka-a 512 kbytes 48 kbytes can module not included r5f563teddfh r5f563teddfh#v0 plqp0112ja-a 512 kbytes 48 kbytes can module not included r5f563teddfp r5f563teddfp#v0 plqp0100kb-a 512 kbytes 48 kbytes can module not included
r01ds0087ej0220 rev.2.20 page 11 of 186 mar 31, 2016 rx63t group 1. overview rx63t r5f563tcddfb r5f563tcddfb#v0 plqp0144ka-a 384 kbytes 32 kbytes can module not included vcc/ pllvcc 4.0 to 5.5v vcc_usb 3.0 to 3.6v avcc/ avcc0 4.0 to 5.5v -40 to +85c (d version) r5f563tcddfa r5f563tcddfa#v0 plqp0120ka-a 384 kbytes 32 kbytes can module not included r5f563tcddfh r5f563tcddfh#v0 plqp0112ja-a 384 kbytes 32 kbytes can module not included r5f563tcddfp r5f563tcddfp#v0 plqp0100kb-a 384 kbytes 32 kbytes can module not included r5f563tbddfb r5f563tbddfb#v0 plqp0144ka-a 256 kbytes 24 kbytes can module not included r5f563tbddfa r5f563tbddfa#v0 plqp0120ka-a 256 kbytes 24 kbytes can module not included r5f563tbddfh r5f563tbddfh#v0 plqp0112ja-a 256 kbytes 24 kbytes can module not included r5f563tbddfp r5f563tbddfp#v0 plqp0100kb-a 256 kbytes 24 kbytes can module not included r5f563tebdfb r5f563tebdfb#v0 plqp0144ka-a 512 kbytes 48 kbytes can module included vcc/ pllvcc/ vcc_usb 2.7 to 3.6v avcc/ avcc0 3.0 to 3.6v or 4.0 to 5.5v r5f563tebdfb r5f563tebdfb#v1 plqp0144ka-a 512 kbytes 48 kbytes can module included r5f563tebdfa r5f563tebdfa#v0 plqp0120ka-a 512 kbytes 48 kbytes can module included r5f563tebdfa r5f563tebdfa#v1 plqp0120ka-a 512 kbytes 48 kbytes can module included r5f563tebdfh r5f563tebdfh#v0 plqp0112ja-a 512 kbytes 48 kbytes can module included r5f563tebdfh r5f563tebdfh#v1 plqp0112ja-a 512 kbytes 48 kbytes can module included r5f563tebdfp r5f563tebdfp#v0 plqp0100kb-a 512 kbytes 48 kbytes can module included r5f563tebdfp r5f563tebdfp#v1 plqp0100kb-a 512 kbytes 48 kbytes can module included r5f563tcbdfb r5f563tcbdfb#v0 plqp0144ka-a 384 kbytes 32 kbytes can module included r5f563tcbdfb r5f563tcbdfb#v1 plqp0144ka-a 384 kbytes 32 kbytes can module included r5f563tcbdfa r5f563tcbdfa#v0 plqp0120ka-a 384 kbytes 32 kbytes can module included r5f563tcbdfa r5f563tcbdfa#v1 plqp0120ka-a 384 kbytes 32 kbytes can module included r5f563tcbdfh r5f563tcbdfh#v0 plqp0112ja-a 384 kbytes 32 kbytes can module included r5f563tcbdfh r5f563tcbdfh#v1 plqp0112ja-a 384 kbytes 32 kbytes can module included r5f563tcbdfp r5f563tcbdfp#v0 plqp0100kb-a 384 kbytes 32 kbytes can module included r5f563tcbdfp r5f563tcbdfp#v1 plqp0100kb-a 384 kbytes 32 kbytes can module included r5f563tbbdfb r5f563tbbdfb#v0 plqp0144ka-a 256 kbytes 24 kbytes can module included r5f563tbbdfb r5f563tbbdfb#v1 plqp0144ka-a 256 kbytes 24 kbytes can module included r5f563tbbdfa r5f563tbbdfa#v0 plqp0120ka-a 256 kbytes 24 kbytes can module included r5f563tbbdfa r5f563tbbdfa#v1 plqp0120ka-a 256 kbytes 24 kbytes can module included r5f563tbbdfh r5f563tbbdfh#v0 plqp0112ja-a 256 kbytes 24 kbytes can module included r5f563tbbdfh r5f563tbbdfh#v1 plqp0112ja-a 256 kbytes 24 kbytes can module included table 1.3 list of products (2/4) group part no. order part no. package on-chip rom capacity on-chip ram capacity option operating voltage operating temperature
r01ds0087ej0220 rev.2.20 page 12 of 186 mar 31, 2016 rx63t group 1. overview rx63t r5f563tbbdfp r5f563tbbdfp#v0 plqp0100kb-a 256 kbytes 24 kbytes can module included vcc/ pllvcc/ vcc_usb 2.7 to 3.6v avcc/ avcc0 3.0 to 3.6v or 4.0 to 5.5v -40 to +85c (d version) r5f563tbbdfp r5f563tbbdfp#v1 plqp0100kb-a 256 kbytes 24 kbytes can module included r5f563teedfb r5f563teedfb#v0 plqp0144ka-a 512 kbytes 48 kbytes can module not included r5f563teedfa r5f563teedfa#v0 plqp0120ka-a 512 kbytes 48 kbytes can module not included r5f563teedfh r5f563teedfh#v0 plqp0112ja-a 512 kbytes 48 kbytes can module not included r5f563teedfp r5f563teedfp#v0 plqp0100kb-a 512 kbytes 48 kbytes can module not included r5f563tcedfb r5f563tcedfb#v0 plqp0144ka-a 384 kbytes 32 kbytes can module not included r5f563tcedfa r5f563tcedfa#v0 plqp0120ka-a 384 kbytes 32 kbytes can module not included r5f563tcedfh r5f563tcedfh#v0 plqp0112ja-a 384 kbytes 32 kbytes can module not included r5f563tcedfp r5f563tcedfp#v0 plqp0100kb-a 384 kbytes 32 kbytes can module not included r5f563tbedfb r5f563tbedfb#v0 plqp0144ka-a 256 kbytes 24 kbytes can module not included r5f563tbedfa r5f563tbedfa#v0 plqp0120ka-a 256 kbytes 24 kbytes can module not included r5f563tbedfh r5f563tbedfh#v0 plqp0112ja-a 256 kbytes 24 kbytes can module not included r5f563tbedfp r5f563tbedfp#v0 plqp0100kb-a 256 kbytes 24 kbytes can module not included r5f563t6edfm r5f563t6edfm#v0 plqp0064kb-a 64 kbytes 8 kbytes can module not included vcc/ pllvcc 2.7 to 3.6v avcc0 3.0 to 3.6v r5f563t5edfm r5f563t5edfm#v0 plqp0064kb-a 48 kbytes 8 kbytes can module not included r5f563t4edfm r5f563t4edfm#v0 plqp0064kb-a 32 kbytes 8 kbytes can module not included r5f563t6edfl r5f563t6edfl#v0 PLQP0048KB-A 64 kbytes 8 kbytes can module not included r5f563t5edfl r5f563t5edfl#v0 PLQP0048KB-A 48 kbytes 8 kbytes can module not included r5f563t4edfl r5f563t4edfl#v0 PLQP0048KB-A 32 kbytes 8 kbytes can module not included r5f563teagfb r5f563teagfb#v1 plqp0144ka-a 512 kbytes 48 kbytes can module included vcc/ pllvcc 4.0 to 5.5v vcc_usb 3.0 to 3.6v avcc/ avcc0 4.0 to 5.5v -40 to +105c (g version)* 1 r5f563teagfa r5f563teagfa#v1 plqp0120ka-a 512 kbytes 48 kbytes can module included r5f563teagfh r5f563teagfh#v1 plqp0112ja-a 512 kbytes 48 kbytes can module included r5f563teagfp r5f563teagfp#v1 plqp0100kb-a 512 kbytes 48 kbytes can module included r5f563tcagfb r5f563tcagfb#v1 plqp0144ka-a 384 kbytes 32 kbytes can module included r5f563tcagfa r5f563tcagfa#v1 plqp0120ka-a 384 kbytes 32 kbytes can module included r5f563tcagfh r5f563tcagfh#v1 plqp0112ja-a 384 kbytes 32 kbytes can module included r5f563tcagfp r5f563tcagfp#v1 plqp0100kb-a 384 kbytes 32 kbytes can module included r5f563tbagfb r5f563tbagfb#v1 plqp0144ka-a 256 kbytes 24 kbytes can module included table 1.3 list of products (3/4) group part no. order part no. package on-chip rom capacity on-chip ram capacity option operating voltage operating temperature
r01ds0087ej0220 rev.2.20 page 13 of 186 mar 31, 2016 rx63t group 1. overview note: ? orderable part numbers are current as of when this manual was published. please make sure to refer to the relevant product page on the renesas website for the latest part numbers. note: ? the products with the product id code 1 (ex. r5f563teadfb#v1) are the revised version to t he specification constraints of technical update tx-rx*-a84a / e described. note 1. please contact renesas electronics sales office for derat ing of operation under ta = +85c to +105c. derating is the systematic reduction of load for th e sake of improved reliability. rx63t r5f563tbagfa r5f563tbagfa#v1 plqp0120ka-a 256 kbytes 24 kbytes can module included vcc/ pllvcc 4.0 to 5.5v vcc_usb 3.0 to 3.6v avcc/ avcc0 4.0 to 5.5v -40 to +105c (g version)* 1 r5f563tbagfh r5f563tbagfh#v1 plqp0112ja-a 256 kbytes 24 kbytes can module included r5f563tbagfp r5f563tbagfp#v1 plqp0100kb-a 256 kbytes 24 kbytes can module included r5f563tebgfb r5f563tebgfb#v1 plqp0144ka-a 512 kbytes 48 kbytes can module included vcc/ pllvcc/ vcc_usb 2.7 to 3.6v avcc/ avcc0 3.0 to 3.6v or 4.0 to 5.5v r5f563tebgfa r5f563tebgfa#v1 plqp0120ka-a 512 kbytes 48 kbytes can module included r5f563tebgfh r5f563tebgfh#v1 plqp0112ja-a 512 kbytes 48 kbytes can module included r5f563tebgfp r5f563tebgfp#v1 plqp0100kb-a 512 kbytes 48 kbytes can module included r5f563tcbgfb r5f563tcbgfb#v1 plqp0144ka-a 384 kbytes 32 kbytes can module included r5f563tcbgfa r5f563tcbgfa#v1 plqp0120ka-a 384 kbytes 32 kbytes can module included r5f563tcbgfh r5f563tcbgfh#v1 plqp0112ja-a 384 kbytes 32 kbytes can module included r5f563tcbgfp r5f563tcbgfp#v1 plqp0100kb-a 384 kbytes 32 kbytes can module included r5f563tbbgfb r5f563tbbgfb#v1 plqp0144ka-a 256 kbytes 24 kbytes can module included r5f563tbbgfa r5f563tbbgfa#v1 plqp0120ka-a 256 kbytes 24 kbytes can module included r5f563tbbgfh r5f563tbbgfh#v1 plqp0112ja-a 256 kbytes 24 kbytes can module included r5f563tbbgfp r5f563tbbgfp#v1 plqp0100kb-a 256 kbytes 24 kbytes can module included r5f563t6egfm r5f563t6egfm#v0 plqp0064kb-a 64 kbytes 8 kbytes can module not included vcc/ pllvcc 2.7 to 3.6v avcc0 3.0 to 3.6v r5f563t5egfm r5f563t5egfm#v0 plqp0064kb-a 48 kbytes 8 kbytes can module not included r5f563t4egfm r5f563t4egfm#v0 plqp0064kb-a 32 kbytes 8 kbytes can module not included r5f563t6egfl r5f563t6egfl#v0 PLQP0048KB-A 64 kbytes 8 kbytes can module not included r5f563t5egfl r5f563t5egfl#v0 PLQP0048KB-A 48 kbytes 8 kbytes can module not included r5f563t4egfl r5f563t4egfl#v0 PLQP0048KB-A 32 kbytes 8 kbytes can module not included table 1.3 list of products (4/4) group part no. order part no. package on-chip rom capacity on-chip ram capacity option operating voltage operating temperature
r01ds0087ej0220 rev.2.20 page 14 of 186 mar 31, 2016 rx63t group 1. overview figure 1.1 how to read the product part number type of memory f: flash memory version package type, number of pins, and pin pitch fb: lqfp/144/0.5 fa: lqfp/120/0.5 fh: lqfp/112/0.65 fp: lqfp/100/0.5 fm: lqfp/64/0.5 fl: lqfp/48/0.5 rom and ram data flash capacity e: 512 kbytes/48 kbytes/32 kbytes c: 384 kbytes/32 kbytes/32 kbytes b: 256 kbytes/24 kbytes/32 kbytes 6: 64 kbytes/8 kbytes/8 kbytes 5: 48 kbytes/8 kbytes/8 kbytes 4: 32 kbytes/8 kbytes/8 kbytes group name 3t: rx63t group renesas mcu renesas semiconductor product a: 5-v product, can module included b: 3-v product, can module included d: 5-v product, can module not included e: 3-v product, can module not included series name rx600 series r 5 f 5 6 d f b aet3 d: operating temperature range (-40 to +85c) g: operating temperature range (-40 to +105c) #v 0 form of packing/external pin surface finishing (lead-free) #v: tray/sn (tin) only product id code
r01ds0087ej0220 rev.2.20 page 15 of 186 mar 31, 2016 rx63t group 1. overview 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram icub: interrupt controller dtca: data transfer controller dmaca: dma controller wdta: watchdog timer iwdta: independent watchdog timer crc: crc (cyclic redundancy check) calculator scic, scid: serial communications interface usba: usb 2.0 host/function module rspi: serial peripheral interface can: can module gpt: general pwm timer mtu3: multi-function timer pulse unit 3 poe3: port output enable 3 cmt: compare match timer riic: i 2 c bus interface cac: clock frequency accuracy measurement circuit doc: data operating circuit mpu: memory protection unit operand bus instruction bus clock generation circuit rx cpu ram rom port 0 port 1 port 2 port 3 port 4 port 7 port 9 port a port b port c scic 4 channels wdta riic 2 channels e2 dataflash crc iwdta poe3 cmt 2 channels ( unit 1) cmt 2 channels ( unit 0) rspi x 2 channels dtca dmaca 4ch icub scid 1 channels port d port e gpt 8ch mtu3 8ch sample-and-hold circuits for the pin section 3 channels window comparator 3 channels cac doc can ( optional ) sample-and-hold circuits for the pin section 3 channels window comparator 3 channels 10-bit adc 20 channels *1 10-bit dac 2 channels *1 port 5 port 6 port 8 port g usba *1 port f internal peripheral buses 1 to 6 external bus bsc internal main bus 2 internal main bus 1 mpu 12-bit adc x 8 channels *1 sample-and-hold circuits for the pin section 3 channels window comparator 3 channels programmable gain amplifier 3 channels programmable gain amplifier 3 channels 12-bit adc 4 channels *1 ( unit 0) 12-bit adc 4 channels *1 ( unit 1 ) note 1: numbers of pins and availability of the usb2.0 host /function module, 12-bit a/d conv erter, 10-bit d/a converter, and 10-bit d/a converter di ffer with the package.
r01ds0087ej0220 rev.2.20 page 16 of 186 mar 31, 2016 rx63t group 1. overview 1.4 pin functions table 1.4 lists the pin functions. table 1.4 pin functions (1/5) classifications pin name i/o description power supply vcc ? power supply pin. connect it to the system power supply. connect this pin to vss via a 0.1-f capacitor. the capacitor should be placed close to the pin vcl ? connect this pin to vss via a 0.1- ? f capacitor. the capacitor should be placed close to the pin vss ? ground pin. connect it to the system power supply (0 v) pllvcc ? power supply pin. connect it to the system power supply. pllvss ? ground pin. connect it to the system power supply (0 v) clock xtal output pins for a crystal resonator . an external clock signal can be input through the extal pin extal input bclk output outputs the external bus clock for external devices clock frequency accuracy measurement cacref input input for the trigger signal in measuring accura cy of the clock frequency operating mode control md input pin for setting the oper ating mode. the signal levels on these pins must not be changed during operation system control res# input reset signal input pin. this lsi enters the reset state when this signal goes low emle input input pin for the on-chip emulator enable signal. when the on-chip emulator is used, this pin should be driven high. when not used, it should be driven low on-chip emulator finec input fine interface clock pin fined i/o fine interface pin trst# input on-chip emulator pins. when the emle pin is driven high, these pins are dedicated for the on-chip emulator. tms input tdi input tck input tdo output trclk output this pin outputs the clock for synchronization with the trace data trsync output this pin indicates that out put from the trdata0 to trdata3 pins is valid trdata0 to trdata3 output these pins output the trace information address bus a0 to a19 output output pins for the address data bus d0 to d15 i/o input and output pins for the bidirectional data bus multiplexed bus a0/d0 to a15/d15 i/o address/data multiplexed bus bus control rd# output strobe signal which indi cates that reading from the external bus interface space is in progress wr# output strobe signal which indicates that writing to the external bus interface space is in progress, in 1-write strobe mode wr0# to wr1# output strobe signals which indicate that either group of data bus pins (d7 to d0 and d15 to d8) is valid in writing to the external bus interface space, in byte strobe mode bc0# to bc1# output strobe signals which indicate that either group of data bus pins (d7 to d0 and d15 to d8) is valid in access to the external bus interface space, in 1-write strobe mode ale output address latch signal when address/data multiplexed bus is selected wait# input input pin for wait request signal s in access to the external space cs0# to cs3# output select signals for cs areas
r01ds0087ej0220 rev.2.20 page 17 of 186 mar 31, 2016 rx63t group 1. overview interrupt nmi input non-maskable interrupt request pin irq0 to irq7 input maskable interrupt request pin multi-function timer pulse unit 3 mtioc0a, mtioc0b mtioc0c, mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output/ pwm output pins mtioc1a, mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/ pwm output pins mtioc2a, mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/ pwm output pins mtioc3a, mtioc3b mtioc3c, mtioc3d i/o the tgra3 to tgrd3 input capture input/output compare output/ pwm output pins mtioc4a, mtioc4b mtioc4c, mtioc4d i/o the tgra4 to tgrd4 input capture input/output compare output/ pwm output pins mtic5u, mtic5v mtic5w input the tgru5, tgrv5, and tgrw5 input capture input/dead time compensation input pins mtioc6a, mtioc6b mtioc6c, mtioc6d i/o the tgra6 to tgrd6 input capture input/output compare output/ pwm output pins mtioc7a, mtioc7b mtioc7c, mtioc7d i/o the tgra7 to tgrd7 input capture input/output compare output/ pwm output pins mtclka, mtclkb mtclkc, mtclkd input input pins for external clock port output enable 3 poe0#, poe4# poe8#, poe10# poe11#, poe12# input input pins for request signals to place the mtu/gpt large-current pins in the high impedance state general pwm timer gtioc0a, gtioc0b i/o the gpt0.g tgra and gpt0.gtgrb input capture input/output compare output/pwm output pins. gtioc1a, gtioc1b i/o the gpt1.gtgra and gpt1.gtgrb input capture input/output compare output/pwm output pins. gtioc2a, gtioc2b i/o the gpt2.gtgra and gpt2.gtgrb input capture input/output compare output/pwm output pins. gtioc3a, gtioc3b i/o the gpt3.gtgra and gpt3.gtgrb input capture input/output compare output/pwm output pins. gtetrg0 input external trigger input pin for the gpt0 to gpt3 gtioc4a, gtioc4b i/o the gpt4.gtgra and gpt4.gtgrb input capture input/output compare output/pwm output pins. gtioc5a, gtioc5b i/o the gpt5.gtgra and gpt5.gtgrb input capture input/output compare output/pwm output pins. gtioc6a, gtioc6b i/o the gpt6.gtgra and gpt6.gtgrb input capture input/output compare output/pwm output pins. gtioc7a, gtioc7b i/o the gpt7.gtgra and gpt7.gtgrb input capture input/output compare output/pwm output pins. gtetrg1 input external trigger input pin for the gpt4 to gpt7 table 1.4 pin functions (2/5) classifications pin name i/o description
r01ds0087ej0220 rev.2.20 page 18 of 186 mar 31, 2016 rx63t group 1. overview serial communications interface (scic) asynchronous mode/clock synchronous mode sck0, sck1, sck2, sck3 i/o input/output pins for clock signals. rxd0, rxd1, rxd2, rxd3 input input pins for data reception. txd0, txd1, txd2, txd3 output output pins for data transmission. cts0#, cts1#, cts2#, cts3# input transmit/receive start control input pins rts0#, rts1#, rts2#, rts3# output transmit/receive start control output pins simple i 2 c mode sscl0, sscl1, sscl2, sscl3 i/o input/output pins for the i 2 c clock ssda0, ssda1, ssda2, ssda3 i/o input/output pins for the i 2 c data simple spi mode sck0, sck1, sck2, sck3 i/o input/output pins for the clock smiso0, smiso1, smiso2, smiso3 i/o input/output pins for slave transmit data. smosi0, smosi1, smosi2, smosi3 i/o input/output pins for master transmit data. ss0#, ss1#, ss2#, ss3# input input pins for chip select signals serial communications interface (scid) asynchronous mode/clock synchronous mode sck12 i/o input/output pin for clock signals. rxd12 input input pin for data reception. txd12 output output pin for data transmission. cts12# input transmit/receive start control input pins rts12# output transmit/receive start control output pins simple i 2 c mode sscl12 i/o input/output pins for the i 2 c clock ssda12 i/o input/output pins for the i 2 c data simple spi mode sck12 i/o input/output pins for the clock smiso12 i/o input/output pins for slave transmit data. smosi12 i/o input/output pins for master transmit data. ss12# input input pins for chip select signals extended serial mode rxdx12 input input pin for receive data txdx12 output output pin for transmit data siox12 i/o input/output pin for transfer data i 2 c bus interface scl, scl0, scl1 i/o clock input/out put pin. n-channel open drain can directly drive buses. sda, sda0, sda1 i/o data input/output pin. n-channel open drain can directly drive buses. table 1.4 pin functions (3/5) classifications pin name i/o description
r01ds0087ej0220 rev.2.20 page 19 of 186 mar 31, 2016 rx63t group 1. overview usb 2.0 host/function module vcc_usb input power supply pin for usb vss_usb input ground pin for usb usb0_dp i/o usb internal transceiver d + input and output pins usb0_dm i/o usb internal transceiver d - input and output pins usb0_exicen output low power control signal for otg chip usb0_vbusen output supply enable signal of vbus (5 v) to otg chip usb0_id input mini ab connector id input pin for use in otg operation usb0_dprpd output d+ signal pull-down control pin for use during host operation usb0_drpd output d- signal pull-down control pin for use during host operation usb0_dpupe output d+ signal pull-up control pin for use during function operation usb0_vbus input pin for monitoring usb cable connection usb0_ovrcura, usb0_ovrcurb input pin for detecting external over current can module crx1 input input pins ctx1 output output pins serial peripheral interface rspcka, rspckb i/o clock input/output pins mosia, mosib i/o inputs or outputs data output from the master misoa, misob i/o inputs or outputs data output from the slave ssla0, sslb0 i/o input or output pins for slave selection ssla1 to ssla3 sslb1 to sslb3 output output pins for slave selection 12-bit a/d converter an000 to an007 an100 to an103 input input pins for the analog si gnals to be processed by the a/d converter adtrg0#, adtrg1# input input pins for the external trigger signals that start the a/d conversion cvrefh input input pin for the high-level reference voltage to the comparator cvrefl input input pin for the low-level reference voltage to the comparator 10-bit a/d converter an0 to an19 input input pins fo r the analog signals to be processed by the 10-bit a/d converter adtrg# input input pins for the external trigger signals that start the a/d conversion d/a converter da0, da1 output output pins for the analog signals to be processed by the 10-bit a/d converter analog power supply avcc0 ? analog vo ltage supply pin for the 12-bit a/d converter. connect this pin to vcc if the 12-bit a/d converter is not to be used avss0 ? analog ground pin for the 12-bit a/d converter. connect this pin to vss if the 12-bit a/d converter is not to be used vrefh0 ? reference voltage supply pin for the 12-bit a/d converter. connect this pin to vcc if the 12-bit a/d converter is not to be used vrefl0 ? reference ground pin for the 12-bit a/d converter. connect this pin to vss if the 12-bit a/d converter is not to be used avcc ? analog voltage supply pin for the 10-bit a/d converter and the 10-bit d/a converter. connect this pin to the power supply of the system if the a/d converter and the d/a converter are not to be used. avss ? ground pin for the 10-bit a/d converter and 10-bit d/a converter. connect this pin to the power-supply ground for the system (0 v). vref ? reference-voltage input pin for the 10-bit a/d converter and the 10- bit d/a converter. connect this pin to the power supply for the system if the a/d converter and the d/a converter are not to be used. table 1.4 pin functions (4/5) classifications pin name i/o description
r01ds0087ej0220 rev.2.20 page 20 of 186 mar 31, 2016 rx63t group 1. overview i/o ports p00 to p05 i/o 6-bit input/output pins p10 to p14 i/o 5-bit input/output pins p20 to p26 i/o 7-bit input/output pins p30 to p35 i/o 6-bit input/output pins p40 to p47 input 8-bit input pins p50 to p57 input 8-bit input pins p60 to p65 input 6-bit input pins p70 to p76 i/o 7-bit input/output pins p80 to p82 i/o 3-bit input/output pins p90 to p96 i/o 7-bit input/output pins pa0 to pa6 i/o 7-bit input/output pins pb0 to pb7 i/o 8-bit input/output pins pc0 to pc5 input 6-bit input pins pd0 to pd7 i/o 8-bit input/output pins pe0, pe1, pe3 to pe5 i/o 6-bit input/output pins pe2 input 1-bit input pin pf0 to pf4 i/o 5-bit input/output pins pg0 to pg6 i/o 7-bit input/output pins table 1.4 pin functions (5/5) classifications pin name i/o description
r01ds0087ej0220 rev.2.20 page 21 of 186 mar 31, 2016 rx63t group 1. overview 1.5 pin assignments figure 1.3 to figure 1.8 show the pin assignments. table 1.5 to table 1.10 show the lists of pins and pin functions. figure 1.3 pin assignment (144-pin lqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 p57 p56 p55 p54 p53 p52 p51 p50 p47 p46 p45 p44 p42 p41 p40 avcc0 vrefh0 vrefl0 avss0 p82 p81 vss p80 p12 p11 p10 p05 vcc p04 usb0_dpupe vss_usb usb0_dp p60 p43 usb0_dm pg3 pg5 p90 p91 p92 p93 p94 p95 vss pg6 p96 vcc p34 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pb0 pb1 pb2 pb3 tdo tck tdi pllvss pb4 pllvcc pb5 pb6 pf0 pg4 p35 pb7 p62 pc0 pc1 avss vref avcc pc2 pc3 p64 p65 pc4 pc5 p20 p22 p23 p24 p25 p26 p30 vss p31 vcc p32 p33 p70 p71 p72 p73 p74 p75 p76 pg0 pg2 p63 p21 pg1 vcc_usb emle p03 p02 vss p01 vcl p00 md pe4 pe3 p14 vcc res# xtal vss extal vcc pe2 pe1 pe0 pd7 pd6 vss pd4 pd3 pd2 pd1 pd0 pf4 pf3 pf1 pe5 p13 pf2 pd5 p61 rx63t group plqp0144ka-a (144-pin lqfp) (top view) note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see table 1.5, list of pins and pin functions (144-pin lqfp).
r01ds0087ej0220 rev.2.20 page 22 of 186 mar 31, 2016 rx63t group 1. overview figure 1.4 pin assignment (120-pin lqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 p55 p54 p53 p52 p51 p50 p47 p46 p45 p44 p42 p41 p40 avcc0 vrefh0 vrefl0 avss0 p82 p81 p80 p12 p11 p10 usb0_dpupe vss_usb usb0_dp p60 p43 usb0_dm pg3 pg5 p90 p91 p92 p93 p94 p95 vss pg6 p96 vcc pa0 pa1 pa2 pa3 pa4 pa5 pb0 pb1 pb2 pb3 pllvss pb4 pllvcc pb5 pb6 pf0 pg4 pb7 p62 avss vref avcc p64 p65 p20 p22 p23 p24 p25 p26 p30 vss p31 vcc p32 p33 p70 p71 p72 p73 p74 p75 p76 pg0 pg2 p63 p21 pg1 vcc_usb emle vss p01 vcl p00 md pe4 pe3 res# xtal vss extal vcc pe2 pe1 pe0 pd7 pd6 pd4 pd3 pd2 pd1 pd0 pf3 pf1 pe5 p13 pf2 pd5 p61 rx63t group plqp0120ka-a (120-pin lqfp) (top view) note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see table 1.6, list of pins and pin functions (120-pin lqfp).
r01ds0087ej0220 rev.2.20 page 23 of 186 mar 31, 2016 rx63t group 1. overview figure 1.5 pin assignment (112-pin lqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 p55 p54 p53 p52 p51 p50 p47 p46 p45 p44 p42 p41 p40 avcc0 vrefh0 vrefl0 avss0 p82 p81 p80 p12 p11 p10 p05 p04 p60 p43 pg3 pg5 p90 p91 p92 p93 p94 p95 vss p96 vcc pa0 pa1 pa2 pa3 pa4 pa5 pb0 pb1 pb2 pb3 pllvss pb4 pllvcc pb5 pb6 pg4 pb7 p62 avss vref avcc p64 p65 p20 p22 p23 p24 p30 vss p31 vcc p32 p33 p70 p71 p72 p73 p74 p75 p76 pg0 pg2 p63 p21 pg1 emle vss p01 vcl p00 md pe4 pe3 res# xtal vss extal vcc pe2 pe1 pe0 pd7 pd6 pd4 pd3 pd2 pd1 pd0 pf4 pe5 pf2 pd5 p61 rx63t group plqp0112ja-a (112-pin lqfp) (top view) note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see table 1.7, list of pins and pin functions (112-pin lqfp). pf3
r01ds0087ej0220 rev.2.20 page 24 of 186 mar 31, 2016 rx63t group 1. overview figure 1.6 pin assignment (100-pin lqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p55 p54 p53 p52 p51 p50 p47 p46 p45 p44 p42 p41 p40 avcc0 vrefh0 vrefl0 avss0 p82 p81 p80 p11 p10 p60 p43 p90 p91 p92 p93 p94 p95 vss p96 vcc pa0 pa1 pa2 pa3 pa4 pa5 pb0 pb1 pb2 pb3 pllvss pb4 pllvcc pb5 pb6 pb7 p62 avss vref avcc p64 p65 p20 p22 p23 p24 p30 vss p31 vcc p32 p33 p70 p71 p72 p73 p74 p75 p76 p63 p21 emle vss p01 vcl p00 md pe4 pe3 res# xtal vss extal vcc pe2 pe1 pe0 pd7 pd6 pd4 pd3 pd2 pd1 pd0 pe5 pd5 p61 rx63t group plqp0100kb-a (100-pin lqfp) (top view) note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see table 1.8, list of pins and pin functions (100-pin lqfp).
r01ds0087ej0220 rev.2.20 page 25 of 186 mar 31, 2016 rx63t group 1. overview figure 1.7 pin assignment (64-pin lqfp) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx63t group plqp0064kb-a (64-pin lqfp) ( top view ) p47 p46 p45 p44 p43 p42 p41 p40 avcc0 vrefh0 vrefl0 avss0 p11 p10 pa5 pa4 p22 p23 p24 p30 vss p31 vcc p32 p33 p70 p71 p72 p73 p74 p75 p76 p91 p92 p93 p94 pa2 pa3 pb0 pb1 pb2 pb3 vss pb4 vcc pb5 pb6 pb7 emle p00 vcl p01 md res# xtal vss extal vcc pe2 pd7 pd6 pd5 pd4 pd3 note: ? this figure indicates the power supply pins and i /o port pins. for the pin configuration, see table 1.9, list of pins and pin functions (64-pin lqfp).
r01ds0087ej0220 rev.2.20 page 26 of 186 mar 31, 2016 rx63t group 1. overview figure 1.8 pin assignment (48-pin lqfp) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 40 41 37 38 39 42 43 44 45 46 47 48 rx63t group PLQP0048KB-A (48-pin lqfp) ( top view ) p47 p44 p43 p42 p41 p40 avcc0 vrefh0 vrefl0 avss0 vcl emle p22 p23 p24 vss p30 vcc p70 p71 p72 p73 p74 p75 p76 pa2 pa3 pb0 pb1 pb2 pb3 vss pb4 vcc pb5 pb6 md res# xtal vss extal vcc pe2 pd7 pd6 pd5 pd4 pd3 note: ? this figure indicates the power supply pins and i /o port pins. for the pin configuration, see table 1.10, list of pins and pin functions (48-pin lqfp).
r01ds0087ej0220 rev.2.20 page 27 of 186 mar 31, 2016 rx63t group 1. overview table 1.5 list of pins and pin functions (144-pin lqfp) (1/4) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can, usb) interrupt s12adb, ad, da 144-pin lqfp 1v c c _ u s b 2 pe5 bclk usb0_vbus irq0 3e m l e 4 trsync p03 rxd2/smiso2/sscl2 irq7 5 trdata3 p02 txd2/smosi2/ssda2 6v s s 7 p01 rd# cts0#/rts0#/ss0#/ usb0_drpd 8v c l 9 p00 cs1# cacref 10 md/fined 11 pe4 a10 poe10#/mtclkc irq1 12 pe3 a11 poe11#/mtclkd irq2-ds 13 trdata2 p14 sck2 14 vcc 15 p13 cts2#/rts2#/ss2#/ usb0_vbusen 16 res# 17 xtal 18 vss 19 extal 20 vcc 21 pe2 poe10# nmi 22 pe1 wr0#/wr# cts12#/rts12#/ ss12#/ssla3/sslb3/ usb0_ovrcura 23 pe0 wr1#/bc1#/ wait# ssla2/sslb2/crx1/ usb0_ovrcurb irq7 24 pd7 gtioc0a cts0#/rts0#/ss0#/ ssla1/sslb1/ctx1 25 pd6 gtioc0b ssla0/sslb0 26 pd5 gtioc1a rxd1/smiso1/sscl1 irq6 27 vss 28 pd4 gtioc1b sck1 29 pd3 gtioc2a txd1/smosi1/ssda1 30 pd2 cs2# gtioc2b mosia/mosib/ usb0_id 31 pd1 cs0# gtioc3a misoa/misob/ usb0_exicen 32 pd0 a12 gtioc3b rspcka/rspckb 33 pf4 cs3# 34 pf3 txd1/smosi1/ssda1 35 pf2 cs1# rxd1/smiso1/sscl1 irq5 36 trst# pf1 37 tms pf0 38 pb7 a19 sck12
r01ds0087ej0220 rev.2.20 page 28 of 186 mar 31, 2016 rx63t group 1. overview 39 pb6 a18 rxd12/smiso12/ sscl12/rxdx12/ crx1 irq2 40 pb5 a17 txd12/smosi12/ ssda12/txdx12/ siox12/ ctx1 41 pllvcc 42 pb4 a16 poe8#/ gtetrg0 irq3-ds 43 pllvss 44 tdi rxd1* 1 45 tck/finec 46 tdo txd1* 1 47 pb3 a15 mtioc0a/cacref sck0 48 pb2 mtioc0b txd0/smosi0/ ssda0/sda0 49 pb1 mtioc0c rxd0/smiso0/ sscl0/scl0 irq4 50 pb0 a14 mtioc0d mosia/mosib 51 trdata1 pa6 cs3# cts3#/rts3#/ss3# 52 pa5 mtioc1a rxd0/smiso0/ sscl0/ misoa/misob adtrg1# 53 pa4 mtioc1b txd0/smosi0/ ssda0/smosi0/ rspcka/rspckb adtrg0# 54 pa3 mtioc2a sck0/ssla0/sslb0 55 pa2 mtioc2b rxd2/smiso2/ sscl2/ ssla1/sslb1 56 pa1 mtioc6a txd2/smosi2/ ssda2/smosi2/ ssla2/sslb2 57 pa0 mtioc6c sck2/ssla3/sslb3 58 trdata0 p35 txd3/smosi3/ssda3 59 trclk p34 gtetrg1 rxd3/smiso3/sscl3 irq3 60 vcc 61 p96 a13 poe4# rxd1/smiso1/sscl1 irq4-ds 62 pg6 cs2# sck1 63 vss 64 p95 mtioc6b/gtioc4a txd1/smosi1/ssda1 65 p94 mtioc7a/gtioc5a cts1#/rts1#/ss1# 66 p93 mtioc7b/gtioc6a cts2#/rts2#/ss2# 67 p92 mtioc6d/gtioc4b 68 p91 mtioc7c/gtioc5b 69 p90 mtioc7d/gtioc6b 70 pg5 poe12# sck3 adtrg# 71 pg4 gtioc6b rxd3/smiso3/sscl3 irq6 table 1.5 list of pins and pin functions (144-pin lqfp) (2/4) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can, usb) interrupt s12adb, ad, da 144-pin lqfp
r01ds0087ej0220 rev.2.20 page 29 of 186 mar 31, 2016 rx63t group 1. overview 72 pg3 gtioc6a txd3/smosi3/ssda3 73 pg2 sck2 irq2 74 pg1 gtioc7b rxd2/smiso2/sscl2 irq1 75 pg0 gtioc7a txd2/smosi2/ssda2 irq0 76 p76 d0/[a0/d0] mtioc4d/gtioc2b 77 p75 d1/[a1/d1] mtioc4c/gtioc1b 78 p74 d2/[a2/d2] mtioc3d/gtioc0b 79 p73 d3/[a3/d3] mtioc4b/gtioc2a 80 p72 d4/[a4/d4] mtioc4a/gtioc1a 81 p71 d5/[a5/d5] mtioc3b/gtioc0a 82 p70 d6/[a6/d6] poe0# cts1#/rts1#/ss1# irq5-ds 83 p33 d7/[a7/d7] mtioc3a/mtclka ssla3/sslb3 84 p32 d8/[a8/d8] mtioc3c/mtclkb ssla2/sslb2 85 vcc 86 p31 d9/[a9/d9] mtioc0a/mtclkc ssla1/sslb1 87 vss 88 p30 d10/[a10/ d10] mtioc0b/mtclkd sck0/ssla0/sslb0 89 p26 cs0# txd1/smosi1/ ssda1/sda1 90 p25 cs1# sck1/scl1 91 p24 d11/[a11/d11] cts0#/rts0#/ss0#/ rspcka/rspckb irq4 92 p23 d12/[a12/ d12] cacref txd0/smosi0/ ssda0/mosia/ mosib/ctx1 93 p22 d13/[a13/ d13] rxd0/smiso0/ sscl0/misoa/ misob/crx1 adtrg# 94 p21 d14/[a14/ d14] mtclka irq6-ds adtrg1# 95 p20 d15/[a15/ d15] mtclkb irq7-ds adtrg0# 96 pc5 an19 97 pc4 an18 98 p65 a0/bc0# an5 99 p64 a1 an4 100 pc3 an17 101 pc2 an16 102 avcc 103 vref 104 avss 105 pc1 an15 106 pc0 an14 107 p63 a2 an3 108 p62 a3 an2 109 p61 a4 an1 table 1.5 list of pins and pin functions (144-pin lqfp) (3/4) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can, usb) interrupt s12adb, ad, da 144-pin lqfp
r01ds0087ej0220 rev.2.20 page 30 of 186 mar 31, 2016 rx63t group 1. overview note 1. available for use as sci pin only in boot mode. 110 p60 a5 an0 111 p57 an13 112 p56 an12 113 p55 an11/da1 114 p54 an10/ da0 115 p53 a6 an9 116 p52 a7 an8 117 p51 an7 118 p50 an6 119 p47 an103/ cvrefh 120 p46 an102 121 p45 an101 122 p44 an100 123 p43 an003/ cvrefl 124 p42 an002 125 p41 an001 126 p40 an000 127 avcc0 128 vrefh0 129 vrefl0 130 avss0 131 p82 wait# mtic5u sck12 irq3 132 p81 a8 mtic5v txd12/smosi12/ ssda12/txdx12/ siox12 133 vss 134 p80 a9 mtic5w rxd12/smiso12/ sscl12/rxdx12 irq5 135 p12 cs3# usb0_dprpd 136 p11 ale mtclkc irq1-ds 137 p10 mtclkd irq0-ds 138 p05 cs2#/wait# 139 vcc 140 p04 141 usb0_dpupe 142 vss_usb 143 usb0_dm 144 usb0_dp table 1.5 list of pins and pin functions (144-pin lqfp) (4/4) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can, usb) interrupt s12adb, ad, da 144-pin lqfp
r01ds0087ej0220 rev.2.20 page 31 of 186 mar 31, 2016 rx63t group 1. overview table 1.6 list of pins and pin functions (120-pin lqfp) (1/4) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can, usb) interrupt s12adb, ad, da 120-pin lqfp 1v c c _ u s b 2 pe5 bclk usb0_vbus irq0 3e m l e 4v s s 5 p01 rd# cts0#/rts0#/ss0#/ usb0_drpd 6v c l 7 p00 cs1# cacref 8m d / f i n e d 9 pe4 a10 poe10#/mtclkc irq1 10 pe3 a11 poe11#/mtclkd irq2-ds 11 p13 cts2#/rts2#/ss2#/ usb0_vbusen 12 res# 13 xtal 14 vss 15 extal 16 vcc 17 pe2 poe10# nmi 18 pe1 wr0#/wr# cts12#/rts12#/ ss12#/ssla3/sslb3/ usb0_ovrcura 19 pe0 wr1#/bc1#/ wait# ssla2/sslb2/crx1/ usb0_ovrcurb irq7 20 trst# pd7 gtioc0a cts0#/rts0#/ss0#/ ssla1/sslb1/ctx1 21 tms pd6 gtioc0b ssla0/sslb0 22 tdi pd5 gtioc1a rxd1/smiso1/sscl1 irq6 23 tck/finec pd4 gtioc1b sck1 24 tdo pd3 gtioc2a txd1/smosi1/ssda1 25 pd2 cs2# gtioc2b mosia/mosib/ usb0_id 26 pd1 cs0# gtioc3a misoa/misob/ usb0_exicen 27 pd0 a12 gtioc3b rspcka/rspckb 28 pf3 txd1/smosi1/ssda1 29 pf2 cs1# rxd1/smiso1/sscl1 irq5 30 pf1 31 pf0 32 pb7 a19 sck12 33 pb6 a18 rxd12/smiso12/ sscl12/rxdx12/ crx1 irq2 34 pb5 a17 txd12/smosi12/ ssda12/txdx12/ siox12/ctx1 35 pllvcc 36 pb4 a16 poe8#/gtetrg0 irq3-ds
r01ds0087ej0220 rev.2.20 page 32 of 186 mar 31, 2016 rx63t group 1. overview 37 pllvss 38 pb3 a15 mtioc0a/cacref sck0 39 pb2 mtioc0b txd0/smosi0/ ssda0/sda0 40 pb1 mtioc0c rxd0/smiso0/ sscl0/scl0 irq4 41 pb0 a14 mtioc0d mosia/mosib 42 pa5 mtioc1a rxd0/smiso0/ sscl0/ misoa/misob adtrg1# 43 pa4 mtioc1b txd0/smosi0/ ssda0/rspcka/ rspckb adtrg0# 44 pa3 mtioc2a sck0/ssla0/sslb0 45 pa2 mtioc2b rxd2/smiso2/ sscl2/ ssla1/sslb1 46 pa1 mtioc6a txd2/smosi2/ ssda2/ssla2/sslb2 47 pa0 mtioc6c sck2/ssla3/sslb3 48 vcc 49 p96 a13 poe4# rxd1/smiso1/sscl1 irq4-ds 50 pg6 cs2# sck1 51 vss 52 p95 mtioc6b/gtioc4a txd1/smosi1/ssda1 53 p94 mtioc7a/gtioc5a cts1#/rts1#/ss1# 54 p93 mtioc7b/gtioc6a cts2#/rts2#/ss2# 55 p92 mtioc6d/gtioc4b 56 p91 mtioc7c/gtioc5b 57 p90 mtioc7d/gtioc6b 58 trclk pg5 poe12# sck3 adtrg# 59 trdata3 pg4 gtioc6b rxd3/smiso3/sscl3 irq6 60 trdata2 pg3 gtioc6a txd3/smosi3/ssda3 61 trdata1 pg2 sck2 irq2 62 trdata0 pg1 gtioc7b rxd2/smiso2/sscl2 irq1 63 trsync pg0 gtioc7a txd2/smosi2/ssda2 irq0 64 p76 d0/[a0/d0] mtioc4d/gtioc2b 65 p75 d1/[a1/d1] mtioc4c/gtioc1b 66 p74 d2/[a2/d2] mtioc3d/gtioc0b 67 p73 d3/[a3/d3] mtioc4b/gtioc2a 68 p72 d4/[a4/d4] mtioc4a/gtioc1a 69 p71 d5/[a5/d5] mtioc3b/gtioc0a 70 p70 d6/[a6/d6] poe0# cts1#/rts1#/ss1# irq5-ds 71 p33 d7/[a7/d7] mtioc3a/mtclka ssla3/sslb3 72 p32 d8/[a8/d8] mtioc3c/mtclkb ssla2/sslb2 73 vcc 74 p31 d9/[a9/d9] mtioc0a/mtclkc ssla1/sslb1 table 1.6 list of pins and pin functions (120-pin lqfp) (2/4) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can, usb) interrupt s12adb, ad, da 120-pin lqfp
r01ds0087ej0220 rev.2.20 page 33 of 186 mar 31, 2016 rx63t group 1. overview 75 vss 76 p30 d10/[a10/ d10] mtioc0b/mtclkd sck0/ssla0/sslb0 77 p26 cs0# txd1/smosi1/ ssda1/sda1 78 p25 cs1# sck1/scl1 79 p24 d11/[a11/d11] cts0#/rts0#/ss0#/ rspcka/rspckb irq4 80 p23 d12/[a12/ d12] cacref txd0/smosi0/ ssda0/mosia/ mosib/ctx1 81 p22 d13/[a13/ d13] rxd0/smiso0/ sscl0/misoa/ misob/crx1 adtrg# 82 p21 d14/[a14/ d14] mtclka irq6-ds adtrg1# 83 p20 d15/[a15/ d15] mtclkb irq7-ds adtrg0# 84 p65 a0/bc0# an5 85 p64 a1 an4 86 avcc 87 vref 88 avss 89 p63 a2 an3 90 p62 a3 an2 91 p61 a4 an1 92 p60 a5 an0 93 p55 an11/da1 94 p54 an10/ da0 95 p53 a6 an9 96 p52 a7 an8 97 p51 an7 98 p50 an6 99 p47 an103/ cvrefh 100 p46 an102 101 p45 an101 102 p44 an100 103 p43 an003/ cvrefl 104 p42 an002 105 p41 an001 106 p40 an000 107 avcc0 108 vrefh0 109 vrefl0 110 avss0 table 1.6 list of pins and pin functions (120-pin lqfp) (3/4) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can, usb) interrupt s12adb, ad, da 120-pin lqfp
r01ds0087ej0220 rev.2.20 page 34 of 186 mar 31, 2016 rx63t group 1. overview 111 p82 wait# mtic5u sck12 irq3 112 p81 a8 mtic5v txd12/smosi12/ ssda12/txdx12/ siox12 113 p80 a9 mtic5w rxd12/smiso12/ sscl12/rxdx12 irq5 114 p12 cs3# usb0_dprpd 115 p11 ale mtclkc irq1-ds 116 p10 mtclkd irq0-ds 117 usb0_dpupe 118 vss_usb 119 usb0_dm 120 usb0_dp table 1.6 list of pins and pin functions (120-pin lqfp) (4/4) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can, usb) interrupt s12adb, ad, da 120-pin lqfp
r01ds0087ej0220 rev.2.20 page 35 of 186 mar 31, 2016 rx63t group 1. overview table 1.7 list of pins and pin functions (112-pin lqfp) (1/4) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can) interrupt s12adb, ad, da 112-pin lqfp 1 pe5 bclk irq0 2e m l e 3v s s 4 p01 rd# cts0#/rts0#/ss0# 5v c l 6 p00 cs1# cacref 7m d / f i n e d 8 pe4 a10 poe10#/mtclkc irq1 9 pe3 a11 poe11#/mtclkd irq2-ds 10 res# 11 xtal 12 vss 13 extal 14 vcc 15 pe2 poe10# nmi 16 pe1 wr0#/wr# cts12#/rts12#/ ss12#/ssla3/sslb3 17 pe0 wr1#/bc1#/ wait# ssla2/sslb2/crx1 irq7 18 pd7 gtioc0a cts0#/rts0#/ss0#/ ssla1/sslb1/ctx1 19 pd6 gtioc0b ssla0/sslb0 20 pd5 gtioc1a rxd1/smiso1/sscl1 irq6 21 pd4 gtioc1b sck1 22 pd3 gtioc2a txd1/smosi1/ssda1 23 pd2 cs2# gtioc2b mosia/mosib 24 pd1 cs0# gtioc3a misoa/misob 25 pd0 a12 gtioc3b rspcka/rspckb 26 tdi pf4 cs3# rxd1* 1 27 tck/finec pf3 txd1/smosi1/ssda1 28 tdo pf2 cs1# rxd1/smiso1/ sscl1/txd1* 1 irq5 29 pb7 a19 sck12 30 pb6 a18 rxd12/smiso12/ sscl12/rxdx12/ crx1 irq2 31 pb5 a17 txd12/smosi12/ ssda12/txdx12/ siox12/ctx1 32 pllvcc 33 pb4 a16 poe8#/gtetrg0 irq3-ds 34 pllvss 35 pb3 a15 mtioc0a/cacref sck0 36 pb2 mtioc0b txd0/smosi0/ ssda0/sda0 37 pb1 mtioc0c rxd0/smiso0/ sscl0/scl0 irq4
r01ds0087ej0220 rev.2.20 page 36 of 186 mar 31, 2016 rx63t group 1. overview 38 pb0 a14 mtioc0d mosia/mosib 39 pa5 mtioc1a rxd0/smiso0/ sscl0/ misoa/misob adtrg1# 40 pa4 mtioc1b txd0/smosi0/ ssda0/rspcka/ rspckb adtrg0# 41 pa3 mtioc2a sck0/ssla0/sslb0 42 pa2 mtioc2b rxd2/smiso2/ sscl2/ ssla1/sslb1 43 pa1 mtioc6a txd2/smosi2/ ssda2/ssla2/sslb2 44 pa0 mtioc6c sck2/ssla3/sslb3 45 vcc 46 p96 a13 poe4# rxd1/smiso1/sscl1 irq4-ds 47 vss 48 p95 mtioc6b/ gtioc4a txd1/smosi1/ssda1 49 p94 mtioc7a/ gtioc5a cts1#/rts1#/ss1# 50 p93 mtioc7b/ gtioc6a cts2#/rts2#/ss2# 51 p92 mtioc6d/gtioc4b 52 p91 mtioc7c/gtioc5b 53 p90 mtioc7d/gtioc6b 54 trclk pg5 poe12# sck3 adtrg# 55 trdata3 pg4 gtioc6b rxd3/smiso3/sscl3 irq6 56 trdata2 pg3 gtioc6a txd3/smosi3/ssda3 57 trdata1 pg2 sck2 irq2 58 trdata0 pg1 gtioc7b rxd2/smiso2/sscl2 irq1 59 trsync pg0 gtioc7a txd2/smosi2/ssda2 irq0 60 p76 d0/[a0/d0] mtioc4d/gtioc2b 61 p75 d1/[a1/d1] mtioc4c/gtioc1b 62 p74 d2/[a2/d2] mtioc3d/gtioc0b 63 p73 d3/[a3/d3] mtioc4b/gtioc2a 64 p72 d4/[a4/d4] mtioc4a/gtioc1a 65 p71 d5/[a5/d5] mtioc3b/gtioc0a 66 p70 d6/[a6/d6] poe0# cts1#/rts1#/ss1# irq5-ds 67 p33 d7/[a7/d7] mtioc3a/mtclka ssla3/sslb3 68 p32 d8/[a8/d8] mtioc3c/mtclkb ssla2/sslb2 69 vcc 70 p31 d9/[a9/d9] mtioc0a/mtclkc ssla1/sslb1 71 vss 72 p30 d10/[a10/ d10] mtioc0b/mtclkd sck0/ssla0/sslb0 73 p24 d11/[a11/d11] cts0#/rts0#/ss0#/ rspcka/rspckb irq4 table 1.7 list of pins and pin functions (112-pin lqfp) (2/4) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can) interrupt s12adb, ad, da 112-pin lqfp
r01ds0087ej0220 rev.2.20 page 37 of 186 mar 31, 2016 rx63t group 1. overview 74 p23 d12/[a12/ d12] cacref txd0/smosi0/ ssda0/mosia/ mosib/ctx1 75 p22 d13/[a13/ d13] rxd0/smiso0/ sscl0/misoa/ misob/crx1 adtrg# 76 p21 d14/[a14/ d14] mtclka irq6-ds adtrg1# 77 p20 d15/[a15/ d15] mtclkb irq7-ds adtrg0# 78 p65 a0/bc0# an5 79 p64 a1 an4 80 avcc 81 vref 82 avss 83 p63 a2 an3 84 p62 a3 an2 85 p61 a4 an1 86 p60 a5 an0 87 p55 an11/da1 88 p54 an10/ da0 89 p53 a6 an9 90 p52 a7 an8 91 p51 an7 92 p50 an6 93 p47 an103/ cvrefh 94 p46 an102 95 p45 an101 96 p44 an100 97 p43 an003/ cvrefl 98 p42 an002 99 p41 an001 100 p40 an000 101 avcc0 102 vrefh0 103 vrefl0 104 avss0 105 p82 wait# mtic5u sck12 irq3 106 p81 a8 mtic5v txd12/smosi12/ ssda12/txdx12/ siox12 107 p80 a9 mtic5w rxd12/smiso12/ sscl12/rxdx12 irq5 108 p12 cs3# 109 p11 ale mtclkc irq1-ds table 1.7 list of pins and pin functions (112-pin lqfp) (3/4) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can) interrupt s12adb, ad, da 112-pin lqfp
r01ds0087ej0220 rev.2.20 page 38 of 186 mar 31, 2016 rx63t group 1. overview note 1. available for use as sci pin only in boot mode. 110 p10 mtclkd irq0-ds 111 trst# p05 wait#/cs2# 112 tms p04 table 1.7 list of pins and pin functions (112-pin lqfp) (4/4) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can) interrupt s12adb, ad, da 112-pin lqfp
r01ds0087ej0220 rev.2.20 page 39 of 186 mar 31, 2016 rx63t group 1. overview table 1.8 list of pins and pin functions (100-pin lqfp) (1/3) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can) interrupt s12adb, ad, da 100-pin lqfp 1 pe5 bclk irq0 2e m l e 3v s s 4 p01 rd# cts0#/rts0#/ss0# 5v c l 6 p00 cs1# cacref 7m d / f i n e d 8 pe4 a10 poe10#/mtclkc irq1 9 pe3 a11 poe11#/mtclkd irq2-ds 10 res# 11 xtal 12 vss 13 extal 14 vcc 15 pe2 poe10# nmi 16 pe1 wr0#/wr# cts12#/rts12#/ ss12#/ssla3/sslb3 17 pe0 wr1#/bc1#/ wait# ssla2/sslb2/crx1 irq7 18 trst# pd7 gtioc0a cts0#/rts0#/ss0#/ ssla1/sslb1/ctx1 19 tms pd6 gtioc0b ssla0/sslb0 20 tdi pd5 gtioc1a rxd1/smiso1/sscl1 irq6 21 tck/finec pd4 gtioc1b sck1 22 tdo pd3 gtioc2a txd1/smosi1/ssda1 23 pd2 cs2# gtioc2b mosia/mosib 24 pd1 cs0# gtioc3a misoa/misob 25 pd0 a12 gtioc3b rspcka/rspckb 26 pb7 a19 sck12 27 pb6 a18 rxd12/smiso12/ sscl12/rxdx12/ crx1 irq2 28 pb5 a17 txd12/smosi12/ ssda12/txdx12/ siox12/ctx1 29 pllvcc 30 pb4 a16 poe8#/gtetrg0 irq3-ds 31 pllvss 32 pb3 a15 mtioc0a/cacref sck0 33 pb2 mtioc0b txd0/smosi0/ ssda0/sda0 34 pb1 mtioc0c rxd0/smiso0/ sscl0/scl0 irq4 35 pb0 a14 mtioc0d mosia/mosib 36 pa5 mtioc1a rxd0/smiso0/ sscl0/ misoa/misob adtrg1#
r01ds0087ej0220 rev.2.20 page 40 of 186 mar 31, 2016 rx63t group 1. overview 37 pa4 mtioc1b txd0/smosi0/ ssda0/ rspcka/rspckb adtrg0# 38 pa3 mtioc2a sck0/ssla0/sslb0 39 pa2 mtioc2b rxd2/smiso2/ sscl2/ ssla1/sslb1 40 pa1 mtioc6a txd2/smosi2/ ssda2/ ssla2/sslb2 41 pa0 mtioc6c sck2/ssla3/sslb3 42 vcc 43 p96 a13 poe4# rxd1/smiso1/sscl1 irq4-ds 44 vss 45 p95 mtioc6b/gtioc4a txd1/smosi1/ssda1 46 p94 mtioc7a/gtioc5a cts1#/rts1#/ss1# 47 p93 mtioc7b/gtioc6a cts2#/rts2#/ss2# 48 p92 mtioc6d/gtioc4b 49 p91 mtioc7c/gtioc5b 50 p90 mtioc7d/gtioc6b 51 p76 d0/[a0/d0] mtioc4d/gtioc2b 52 p75 d1/[a1/d1] mtioc4c/gtioc1b 53 p74 d2/[a2/d2] mtioc3d/gtioc0b 54 p73 d3/[a3/d3] mtioc4b/gtioc2a 55 p72 d4/[a4/d4] mtioc4a/gtioc1a 56 p71 d5/[a5/d5] mtioc3b/gtioc0a 57 p70 d6/[a6/d6] poe0# cts1#/rts1#/ss1# irq5-ds 58 p33 d7/[a7/d7] mtioc3a/mtclka ssla3/sslb3 59 p32 d8/[a8/d8] mtioc3c/mtclkb ssla2/sslb2 60 vcc 61 p31 d9/[a9/d9] mtioc0a/mtclkc ssla1/sslb1 62 vss 63 p30 d10/[a10/ d10] mtioc0b/mtclkd sck0/ssla0/sslb0 64 p24 d11/[a11/d11] cts0#/rts0#/ss0#/ rspcka/rspckb irq4 65 p23 d12/[a12/ d12] cacref txd0/smosi0/ ssda0/mosia/ mosib/ctx1 66 p22 d13/[a13/ d13] rxd0/smiso0/ sscl0/misoa/ misob/crx1 adtrg# 67 p21 d14/[a14/ d14] mtclka irq6-ds adtrg1# 68 p20 d15/[a15/ d15] mtclkb irq7-ds adtrg0# 69 p65 a0/bc0# an5 70 p64 a1 an4 table 1.8 list of pins and pin functions (100-pin lqfp) (2/3) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can) interrupt s12adb, ad, da 100-pin lqfp
r01ds0087ej0220 rev.2.20 page 41 of 186 mar 31, 2016 rx63t group 1. overview 71 avcc 72 vref 73 avss 74 p63 a2 an3 75 p62 a3 an2 76 p61 a4 an1 77 p60 a5 an0 78 p55 an11/da1 79 p54 an10/ da0 80 p53 a6 an9 81 p52 a7 an8 82 p51 an7 83 p50 an6 84 p47 an103/ cvrefh 85 p46 an102 86 p45 an101 87 p44 an100 88 p43 an003/ cvrefl 89 p42 an002 90 p41 an001 91 p40 an000 92 avcc0 93 vrefh0 94 vrefl0 95 avss0 96 p82 wait# mtic5u sck12 irq3 97 p81 a8 mtic5v txd12/smosi12/ ssda12/txdx12/ siox12 98 p80 a9 mtic5w rxd12/smiso12/ sscl12/rxdx12 irq5 99 p11 ale mtclkc irq1-ds 100 p10 mtclkd irq0-ds table 1.8 list of pins and pin functions (100-pin lqfp) (3/3) pin number power supply clock system control i/o port bus timer (mtu3, gpt, poe3, cac) communications (scic, scid, rspi, riic, can) interrupt s12adb, ad, da 100-pin lqfp
r01ds0087ej0220 rev.2.20 page 42 of 186 mar 31, 2016 rx63t group 1. overview table 1.9 list of pins and pin functions (64-pin lqfp) (1/3) pin number power supply clock system control i/o port poe3 timer communications interrupt s12adb 64-pin lqfp (mtu3, gpt, cac) (scic, scid) (rspi, riic) 1e m l e 2 p00 gtioc3a cts0# rts0# ss0# irq2-ds 3v c l 4p 0 1g t i o c 3 b cacref irq4-ds 5m d fined 6 res# 7x t a l 8v s s 9e x t a l 10 vcc 11 pe2 poe10# nmi 12 trst# pd7 gtioc0a cts0# rts0# ss0# 13 tms pd6 gtioc0b 14 tdi pd5 gtioc1a rxd1 smiso1 sscl1 15 tck finec pd4 gtioc1b sck1 16 tdo pd3 gtioc2a txd1 smosi1 ssda1 17 pb7 gtioc2b sck12 18 pb6 gtioc2b rxd12 smiso12 sscl12 rxdx12 19 pb5 poe11# txd12 smosi12 ssda12 txdx12 siox12 irq0 20 vcc 21 pb4 poe8# gtetrg cts12# rts12# ss12# irq3-ds 22 vss 23 pb3 mtioc0a mtclka cacref sck0 24 pb2 mtioc0b mtclkb txd0 smosi0 ssda0 sda 25 pb1 mtioc0c rxd0 smiso0 sscl0 scl 26 pb0 mtioc0d mosia
r01ds0087ej0220 rev.2.20 page 43 of 186 mar 31, 2016 rx63t group 1. overview 27 pa3 mtioc2a ssla0 28 pa2 mtioc2b ssla1 29 p94 txd1 smosi1 ssda1 30 p93 rxd1 smiso1 sscl1 irq1 31 p92 sck1 32 p91 cts1# rts1# ss1# 33 p76 mtioc4d gtioc2b mtioc7d 34 p75 mtioc4c gtioc1b mtioc7c 35 p74 mtioc3d gtioc0b mtioc6d 36 p73 mtioc4b gtioc2a mtioc7b 37 p72 mtioc4a gtioc1a mtioc7a 38 p71 mtioc3b gtioc0a mtioc6b 39 p70 poe0# cts1# rts1# ss1# irq5-ds 40 p33 mtioc3a mtioc6a ssla3 41 p32 mtioc3c mtioc6c ssla2 42 vcc 43 p31 mtioc0a ssla1 44 vss 45 p30 mtioc0b mtclkd txd0 smosi0 ssda0 ssla0 46 p24 mtic5u mtclkc rxd0 smiso0 sscl0 rspcka 47 p23 mtic5v mtclkb cacref sck0 mosia 48 p22 mtic5w mtclka cts0# rts0# ss0# misoa 49 p47 an007 cvrefh table 1.9 list of pins and pin functions (64-pin lqfp) (2/3) pin number power supply clock system control i/o port poe3 timer communications interrupt s12adb 64-pin lqfp (mtu3, gpt, cac) (scic, scid) (rspi, riic)
r01ds0087ej0220 rev.2.20 page 44 of 186 mar 31, 2016 rx63t group 1. overview 50 p46 an006 51 p45 an005 52 p44 an004 53 p43 an003 cvrefl 54 p42 an002 55 p41 an001 56 p40 an000 57 avcc0 58 vrefh0 59 vrefl0 60 avss0 61 p11 mtclkc irq1-ds 62 p10 mtclkd irq0-ds 63 pa5 mtioc1a misoa 64 pa4 mtioc1b rspcka adtrg0# table 1.9 list of pins and pin functions (64-pin lqfp) (3/3) pin number power supply clock system control i/o port poe3 timer communications interrupt s12adb 64-pin lqfp (mtu3, gpt, cac) (scic, scid) (rspi, riic)
r01ds0087ej0220 rev.2.20 page 45 of 186 mar 31, 2016 rx63t group 1. overview table 1.10 list of pins and pin functions (48-pin lqfp) (1/2) pin number power supply clock system control i/o port poe3 timer communications interrupt s12adb 64-pin lqfp (mtu3, gpt, cac) (scic, scid) (rspi, riic) 1m d fined 2 res# 3x t a l 4v s s 5e x t a l 6v c c 7 pe2 poe10# nmi 8 trst# pd7 gtioc0a cts0# rts0# ss0# 9t m sp d 6 g t i o c 0 b 10 tdi pd5 gtioc1a rxd1 smiso1 sscl1 11 tck finec pd4 gtioc1b sck1 12 tdo pd3 gtioc2a txd1 smosi1 ssda1 13 pb6 gtioc2b rxd12 smiso12 sscl12 rxdx12 14 pb5 poe11# txd12 smosi12 ssda12 txdx12 siox12 irq0 15 vcc 16 pb4 poe8# gtetrg cts12# rts12# ss12# irq3-ds 17 vss 18 pb3 mtioc0a mtclka cacref sck0 19 pb2 mtioc0b mtclkb txd0 smosi0 ssda0 sda 20 pb1 mtioc0c rxd0 smiso0 sscl0 scl 21 pb0 mtioc0d mosia 22 pa3 mtioc2a ssla0 23 pa2 mtioc2b ssla1 24 p76 mtioc4d gtioc2b mtioc7d 25 p75 mtioc4c gtioc1b mtioc7c
r01ds0087ej0220 rev.2.20 page 46 of 186 mar 31, 2016 rx63t group 1. overview 26 p74 mtioc3d gtioc0b mtioc6d 27 p73 mtioc4b gtioc2a mtioc7b 28 p72 mtioc4a gtioc1a mtioc7a 29 p71 mtioc3b gtioc0a mtioc6b 30 p70 poe0# cts1# rts1# ss1# irq5-ds 31 vcc 32 p30 mtioc0b mtclkd txd0 smosi0 ssda0 ssla0 33 vss 34 p24 mtic5u mtclkc rxd0 smiso0 sscl0 rspcka 35 p23 mtic5v mtclkb cacref sck0 mosia 36 p22 mtic5w mtclka cts0# rts0# ss0# misoa 37 p47 an007 cvrefh 38 p44 an004 39 p43 an003 cvrefl 40 p42 an002 41 p41 an001 42 p40 an000 43 avcc0 44 vrefh0 45 vrefl0 46 avss0 47 vcl 48 emle table 1.10 list of pins and pin functions (48-pin lqfp) (2/2) pin number power supply clock system control i/o port poe3 timer communications interrupt s12adb 64-pin lqfp (mtu3, gpt, cac) (scic, scid) (rspi, riic)
r01ds0087ej0220 rev.2.20 page 47 of 186 mar 31, 2016 rx63t group 2. cpu 2. cpu the rx cpu has sixteen general-purpose registers, nine control registers, and one accumulator used for dsp instructions. figure 2.1 register set of the cpu note 1. the stack pointer (sp) can be the interrupt stack pointer (isp) or user stack pointer (usp), according to the value of the u bit in the psw. usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) fpsw (floating-point status word) r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp)* 1 general-purpose register control register b31 b0 b31 b0 dsp instruction register b63 b0 acc (accumulator)
r01ds0087ej0220 rev.2.20 page 48 of 186 mar 31, 2016 rx63t group 2. cpu 2.1 general-purpose r egisters (r0 to r15) this cpu has sixteen general-purpose registers (r0 to r15). r1 to r15 can be used as data registers or address registers. r0, a general-purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by the value of the stack pointer select bit (u) in the processor status word (psw). 2.2 control registers (1) interrupt stack pointer (i sp)/user stack pointer (usp) the stack pointer (sp) can be either of two types, the interrupt stack point er (isp) or the user stack pointer (usp). whether the stack pointer operates as the isp or usp depends on the value of the stack poi nter select bit (u) in the processor status word (psw). set the isp or usp to a multiple of four, as this reduces th e numbers of cycles required to execute interrupt sequences and instructions entai ling stack manipulation. (2) interrupt table register (intb) the interrupt table register (intb) specifies the address where the relocatable vector table starts. (3) program counter (pc) the program counter (pc) indicates the a ddress of the instruction being executed. (4) processor status word (psw) the processor status word (psw) i ndicates the results of instruction execution or the state of the cpu. (5) backup pc (bpc) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the program counter (pc) are saved in the bpc register. (6) backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw ) are saved in the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. (7) fast interrupt vector register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a bran ch destination address when a fa st interrupt has been generated. (8) floating-point status word (fpsw) the floating-point status word (fpsw) indicates the results of floating-point operations. when an exception handling enable bit (e j) enables the exception handling (ej = 1) , the exception cause can be identified by checking the corresponding cj flag in the exception handling routine. if th e exception handling is masked (ej = 0), the occurrence of exception can be ch ecked by reading the fj flag at the end of a series of pro cessing. once the fj flag has been set to 1, this value is retained until it is cleared to 0 by software (j = x, u, z, o, or v).
r01ds0087ej0220 rev.2.20 page 49 of 186 mar 31, 2016 rx63t group 2. cpu 2.2.1 register associat ed with dsp instructions (1) accumulator (acc) the accumulator (acc) is a 64-bit register used for dsp instru ctions. the accumulator is also used for the multiply and multiply-and-accumulate instructions; em ul, emulu, fmul, mul, and rmpa, in which case the prior value in the accumulator is modified by execution of the instruction. use the mvtachi and mvtaclo instructions for wr iting to the accumulator. the mvtachi and mvtaclo instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfachi and mvfacmi instructions for reading data from th e accumulator. the mvfachi and mvfacmi instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
r01ds0087ej0220 rev.2.20 page 50 of 186 mar 31, 2016 rx63t group 3. address space 3. address space 3.1 address space this mcu has a 4-gbyte address space, consisting of the range of addresses from 0000 0000h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is po ssible, and this contains bo th program and data areas. figure 3.1 shows the memory maps in the re spective operating modes. accessible areas will differ according to the operating mode and states of control bits.
r01ds0087ej0220 rev.2.20 page 51 of 186 mar 31, 2016 rx63t group 3. address space figure 3.1 memory map in each operating mode reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 on-chip ram* 2 external address space peripheral i/o registers reserved area* 3 reserved area* 3 external address space on-chip ram* 2 on-chip rom (program rom) (read only)* 2 peripheral i/o registers on-chip rom (e2 data flash) on-chip rom (program rom) (write only) reserved area* 3 on-chip rom (e2 data flash) reserved area* 3 on-chip rom (e2 data flash) reserved area* 3 external address space reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 0000 0000h 0008 0000h ffff ffffh single-chip mode* 1 on-chip ram* 2 on-chip rom (program rom) (read only)* 2 0010 0000h peripheral i/o registers 0010 8000h on-chip rom (e2 data flash) 0080 0000h 0100 0000h on-chip rom (program rom) (write only) fff8 0000h on-chip rom (user boot) (read only) peripheral i/o registers 007f c000h 007f c500h 007f fc00h 0000 c000h 0000 0000h 0008 0000h on-chip rom enabled extended mode 0010 0000h 0010 8000h 0080 0000h 0100 0000h 0800 0000h 007f c000h 007f c500h 007f fc00h 0000 c000h 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode 0010 0000h 0500 0000h 0800 0000h ff00 0000h 0000 c000h 00f8 0000h 00f8 0000h peripheral i/o registers ff7f c000h ffff ffffh fff8 0000h ff80 0000h on-chip rom (user boot) (read only) ff7f c000h ff80 0000h 0500 0000h note 1. the address space in boot mode and user boot mode is the same as the address space in single-chip mode. note 2. the capacity of rom/ram differs depending on the products. note:?see table 1.3, list of products, for the product type name. note 3. reserved areas should not be accessed. note 4. for details on the fcu, see section 41, flash memory in the user?s manual: hardware. rom (bytes) ram (bytes) e2 dataflash (bytes) capacity address capacity address capacity address 512 k fff8 0000h to ffff ffffh 48 k 0000 0000h to 0000 bfffh 32 k 0010 0000h to 0010 8000h 384 k fffa 0000h to ffff ffffh 32 k 0000 0000h to 0000 7fffh 256 k fffc 0000h to ffff ffffh 24 k 0000 0000h to 0000 5fffh 64 k ffff 0000h to ffff ffffh 8 k 0000 0000h to 0000 1fffh 8 k 0010 0000h to 0010 2000h 48 k ffff 4000h to ffff ffffh 32 k ffff 8000h to ffff ffffh
r01ds0087ej0220 rev.2.20 page 52 of 186 mar 31, 2016 rx63t group 3. address space 3.2 external address space the external address space is divided into up to four cs areas (cs0 to cs3) , each corresponding to the csn# signal output from a csn# (n = 0 to 3) pin. figure 3.2 shows the address ranges corresponding to the indivi dual cs areas (cs0 to cs3) in on-chip rom disabled extended mode. figure 3.2 correspondence between external address spaces and cs areas (in on-chip rom disabl ed extended mode) reserved area* 1 reserved area* 1 cs3 (1 mbytes) reserved area* 1 cs2 (1 mbytes) reserved area* 1 cs1 (1 mbytes) cs0 (1 mbytes) on-chip ram external address space reserved area* 1 peripheral i/o registers reserved area* 1 reserved area* 1 external address space* 2 0000 0000h 0008 0000h 0010 0000h 0500 0000h 0800 0000h ff00 0000h 0000 c000h 0500 0000h 05f0 0000h 0600 0000h 06f0 0000h 0700 0000h 07f0 0000h 05ef ffffh 05ff ffffh 06ef ffffh 06ff ffffh 07ef ffffh 07ff ffffh ffff ffffh ffff ffffh ff00 0000h fff0 0000h ffef ffffh note 1. reserved areas should not be accessed. note 2. the cs0 area is disabled in on-chip rom enabled extended mode. in this mode, the address space for addresses abov e 0800 0000h is as shown in figure 3.1, memory map in each operating mode.
r01ds0087ej0220 rev.2.20 page 53 of 186 mar 31, 2016 rx63t group 4. i/o registers 4. i/o registers this section gives information on the on-chip i/o register addr esses. the information is given as shown below. notes on writing to registers are also given at the end. (1) i/o register addresses (address order) ? registers are listed from th e lower allocation addresses. ? registers are classified acco rding to module symbols. ? the number of access cycles indicates the number of cycles based on the specified reference clock. ? among the internal i/o register area, a ddresses not listed in the list of regi sters are reserved. reserved addresses must not be accessed. do not access these addresses; ot herwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. (2) notes on writing to i/o registers when writing to an i/o re gister, the cpu starts executing the subsequent in struction before completing i/o register write. this may cause the subsequent instruction to be executed befo re the post-update i/o register value is reflected on the operation. as described in the following examples, sp ecial care is required for the cases in wh ich the subsequent instruction must be executed after the post-update i/o re gister value is actually reflected. [examples of cases requiring special care] ? the subsequent instruction must be execu ted while an interrupt request is disabled with the ienj bit in iern of the icu (interrupt request enab le bit) cleared to 0. ? a wait instruction is executed immediately after the preprocessing for causing a transition to the low power consumption state. in the above cases, after writing to an i/o register, wait until the write operation is completed using the following procedure and then execute the subsequent instruction. (a) write to an i/o register. (b) read the value from the i/o re gister to a general register. (c) execute the operati on using the value read. (d) execute the subsequent instruction. [instruction examples] ? byte-size i/o registers mov.l #sfr_addr, r1 mov.b #sfr_data, [r1] cmp [r1].ub, r1 ;; next process ? word-size i/o registers mov.l #sfr_addr, r1 mov.w #sfr_data, [r1] cmp [r1].w, r1 ;; next process
r01ds0087ej0220 rev.2.20 page 54 of 186 mar 31, 2016 rx63t group 4. i/o registers ? longword-size i/o registers mov.l #sfr_addr, r1 mov.l #sfr_data, [r1] cmp [r1].l, r1 ;; next process if multiple registers are written to and a subsequent instruc tion should be executed after th e write operati ons are entirely completed, only read the i/o register that was last written to and execute the operation using th e value; it is not necessary to read or execute operation for all the registers that were written to. (3) number of access cycles to i/o registers for the number of i/o regist er access cycles, refer to table 4.1, list of i/o registers (address order) . the number of access cycles to i/o regist ers is obtained by following equation. * 1 number of access cycles to i/o registers = numb er of bus cycles for internal main bus 1 + number of divided clock synchronization cycles + number of bus cycles for inte rnal peripheral bus 1 to 6 the number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed. when peripheral functions connected to internal peripheral bus 2 to 6 ar e accessed, the number of divided clock synchronization cycles is added. the number of divided clock synchronization cycles differs depending on the frequency ratio between iclk and pclk (or fclk, bclk) or bus access timing. in the peripheral function unit, when the fr equency ratio of iclk is equal to or gr eater than that of pclk (or fclk), the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of pclk (or fclk) at a maximum. therefore, one pclk (or fclk) has been added to the number of access states shown in table 4.1 . when the frequency ratio of iclk is lower than that of pclk (or fclk), the subsequent bus access is started from the iclk cycle following the completion of the access to the peripheral functions. th erefore, the access cycles are described on an iclk basis. in the external bus control unit, the sum of the number of bu s cycles for internal main bus 1 and the number of divided clock synchronization cycles will be one cycle of bclk at a maximum. therefore, one bclk is added to the number of access cycles shown in table 4.1 . note 1. this applies to the number of cycles when the access from th e cpu does not conflict with the instruction fetching to the external memory or bus access from the different bus master (dmac or dtc). (4) note on sleep mode and mode transition during sleep mode or a mode transition, do not write to the system control related register s (indicated by 'system' in the module symbol column in table 4.1, list of i/o registers (address order) ).
r01ds0087ej0220 rev.2.20 page 55 of 186 mar 31, 2016 rx63t group 4. i/o registers 4.1 i/o register addresses (address order) table 4.1 list of i/o regist ers (address order) (1/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk 0008 0000h system mode monitor register mdmonr 16 16 3 iclk operating modes 0008 0002h system mode status register mdsr 16 16 3 iclk not present in versions with 64 or 48 pins. 0008 0006h system system control register 0 syscr0 16 16 3 iclk 0008 0008h system system control register 1 syscr1 16 16 3 iclk 0008 000ch system standby control register sbycr 16 16 3 iclk low power consumption 0008 0010h system module stop control register a mstpcra 32 32 3 iclk 0008 0014h system module stop control register b mstpcrb 32 32 3 iclk 0008 0018h system module stop control register c mstpcrc 32 32 3 iclk 0008 0020h system system clock control register sckcr 32 32 3 iclk clock generation circuit 0008 0024h system system clock control register 2 sckcr2 16 16 3 iclk not present in versions with 64 or 48 pins. 0008 0026h system system clock control register 3 sckcr3 16 16 3 iclk 0008 0028h system pll control register pllcr 16 16 3 iclk 0008 002ah system pll control register 2 pllcr2 8 8 3 iclk 0008 0030h system external bus clock control regi ster bckcr 8 8 3 iclk not present in versions with 64 or 48 pins. 0008 0032h system main clock oscillator control register mosccr 8 8 3 iclk 0008 0034h system low-speed on-chip oscillator control register lococr 8 8 3 iclk 0008 0035h system iwdt-dedicated on-chip oscillator control register ilococr 8 8 3 iclk 0008 0040h system oscillation stop detection control register ostdcr 8 8 3 iclk 0008 0041h system oscillation stop detection status register ostdsr 8 8 3 iclk 0008 00a2h system main clock oscillator wait control register moscwtcr 8 8 3 iclk low power consumption 0008 00a6h system pll wait control register pllwtcr 8 8 3 iclk 0008 00c0h system reset status register 2 rstsr2 8 8 3 iclk resets 0008 00c2h system software reset register swrr 16 16 3 iclk 0008 00e0h system voltage monitoring 1 circuit control register 1 lvd1cr1 8 8 3 iclk lvda 0008 00e1h system voltage monitoring 1 circuit status register lvd1sr 8 8 3 iclk 0008 00e2h system voltage monitoring 2 circuit control register 1 lvd2cr1 8 8 3 iclk 0008 00e3h system voltage monitoring 2 circuit status register lvd2sr 8 8 3 iclk 0008 03feh system protect register prcr 16 16 3 iclk register write protection function 0008 1300h bsc bus error status clear register berclr 8 8 2 iclk buses 0008 1304h bsc bus error monitoring enable register beren 8 8 2 iclk 0008 1308h bsc bus error status register 1 bersr1 8 8 2 iclk 0008 130ah bsc bus error status register 2 bersr2 16 16 2 iclk 0008 1310h bsc bus priority control register buspri 16 16 2 iclk 0008 2000h dmac0 dma source address register dmsar 32 32 2 iclk dmaca 0008 2004h dmac0 dma destination address register dmdar 32 32 2 iclk 0008 2008h dmac0 dma transfer count register dmcra 32 32 2 iclk 0008 200ch dmac0 dma block transfer count register dmcrb 16 16 2 iclk 0008 2010h dmac0 dma transfer mode register dmtmd 16 16 2 iclk 0008 2013h dmac0 dma interrupt setting register dmint 8 8 2 iclk 0008 2014h dmac0 dma address mode register dmamd 16 16 2 iclk 0008 2018h dmac0 dma offset register dmofr 32 32 2 iclk 0008 201ch dmac0 dma transfer enable register dmcnt 8 8 2 iclk 0008 201dh dmac0 dma software start register dmreq 8 8 2 iclk 0008 201eh dmac0 dma status register dmsts 8 8 2 iclk
r01ds0087ej0220 rev.2.20 page 56 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 201fh dmac0 dma activation source flag control register dmcsl 8 8 2 iclk dmaca 0008 2040h dmac1 dma source address register dmsar 32 32 2 iclk 0008 2044h dmac1 dma destination address register dmdar 32 32 2 iclk 0008 2048h dmac1 dma transfer count register dmcra 32 32 2 iclk 0008 204ch dmac1 dma block transfer count register dmcrb 16 16 2 iclk 0008 2050h dmac1 dma transfer mode register dmtmd 16 16 2 iclk 0008 2053h dmac1 dma interrupt setting register dmint 8 8 2 iclk 0008 2054h dmac1 dma address mode register dmamd 16 16 2 iclk 0008 205ch dmac1 dma transfer enable register dmcnt 8 8 2 iclk 0008 205dh dmac1 dma software start register dmreq 8 8 2 iclk 0008 205eh dmac1 dma status register dmsts 8 8 2 iclk 0008 205fh dmac1 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2080h dmac2 dma source address register dmsar 32 32 2 iclk 0008 2084h dmac2 dma destination address register dmdar 32 32 2 iclk 0008 2088h dmac2 dma transfer count register dmcra 32 32 2 iclk 0008 208ch dmac2 dma block transfer count register dmcrb 16 16 2 iclk 0008 2090h dmac2 dma transfer mode register dmtmd 16 16 2 iclk 0008 2093h dmac2 dma interrupt setting register dmint 8 8 2 iclk 0008 2094h dmac2 dma address mode register dmamd 16 16 2 iclk 0008 209ch dmac2 dma transfer enable register dmcnt 8 8 2 iclk 0008 209dh dmac2 dma software start register dmreq 8 8 2 iclk 0008 209eh dmac2 dma status register dmsts 8 8 2 iclk 0008 209fh dmac2 dma activation source flag control register dmcsl 8 8 2 iclk 0008 20c0h dmac3 dma source address register dmsar 32 32 2 iclk 0008 20c4h dmac3 dma destination address register dmdar 32 32 2 iclk 0008 20c8h dmac3 dma transfer count register dmcra 32 32 2 iclk 0008 20cch dmac3 dma block transfer count register dmcrb 16 16 2 iclk 0008 20d0h dmac3 dma transfer mode register dmtmd 16 16 2 iclk 0008 20d3h dmac3 dma interrupt setting register dmint 8 8 2 iclk 0008 20d4h dmac3 dma address mode register dmamd 16 16 2 iclk 0008 20dch dmac3 dma transfer enable register dmcnt 8 8 2 iclk 0008 20ddh dmac3 dma software start register dmreq 8 8 2 iclk 0008 20deh dmac3 dma status register dmsts 8 8 2 iclk 0008 20dfh dmac3 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2200h dmac dmaca module activation register dmast 8 8 2 iclk 0008 2400h dtc dtc control register dtccr 8 8 2iclk dtca 0008 2404h dtc dtc vector base register dtcvbr 32 32 2iclk 0008 2408h dtc dtc address mode register dtcadmod 8 8 2iclk 0008 240ch dtc dtc module start register dtcst 8 8 2iclk 0008 240eh dtc dtc status register dtcsts 16 16 2iclk 0008 3002h bsc cs0 mode register cs0mod 16 16 1, 2 bclk buses not present in versions with 64 or 48 pins. 0008 3004h bsc cs0 wait control register 1 cs0wcr1 32 32 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3008h bsc cs0 wait control register 2 cs0wcr2 32 32 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3012h bsc cs1 mode register cs1mod 16 16 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3014h bsc cs1 wait control register 1 cs1wcr1 32 32 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3018h bsc cs1 wait control register 2 cs1wcr2 32 32 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3022h bsc cs2 mode register cs2mod 16 16 1, 2 bclk not present in versions with 64 or 48 pins. table 4.1 list of i/o regist ers (address order) (2/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 57 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 3024h bsc cs2 wait control register 1 cs2wcr1 32 32 1, 2 bclk buses not present in versions with 64 or 48 pins. 0008 3028h bsc cs2 wait control register 2 cs2wcr2 32 32 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3032h bsc cs3 mode register cs3mod 16 16 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3034h bsc cs3 wait control register 1 cs3wcr1 32 32 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3038h bsc cs3 wait control register 2 cs3wcr2 32 32 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3802h bsc cs0 control register cs0cr 16 16 1, 2 bclk not present in versions with 64 or 48 pins. 0008 380ah bsc cs0 recovery cycle register cs0rec 16 16 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3812h bsc cs1 control register cs1cr 16 16 1, 2 bclk not present in versions with 64 or 48 pins. 0008 381ah bsc cs1 recovery cycle register cs1rec 16 16 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3822h bsc cs2 control register cs2cr 16 16 1, 2 bclk not present in versions with 64 or 48 pins. 0008 382ah bsc cs2 recovery cycle register cs2rec 16 16 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3832h bsc cs3 control register cs3cr 16 16 1, 2 bclk not present in versions with 64 or 48 pins. 0008 383ah bsc cs3 recovery cycle register cs3rec 16 16 1, 2 bclk not present in versions with 64 or 48 pins. 0008 3880h bsc cs recovery cycle insertion enable register csrecen 16 16 1, 2 bclk not present in versions with 64 or 48 pins. 0008 6400h mpu region-0 start page number register rspage0 32 32 1 iclk mpu 0008 6404h mpu region-0 end page number register repage0 32 32 1 iclk 0008 6408h mpu region-1 start page number register rspage1 32 32 1 iclk 0008 640ch mpu region-1 end page number register repage1 32 32 1 iclk 0008 6410h mpu region-2 start page number register rspage2 32 32 1 iclk 0008 6414h mpu region-2 end page number register repage2 32 32 1 iclk 0008 6418h mpu region-3 start page number register rspage3 32 32 1 iclk 0008 641ch mpu region-3 end page number register repage3 32 32 1 iclk 0008 6420h mpu region-4 start page number register rspage4 32 32 1 iclk 0008 6424h mpu region-4 end page number register repage4 32 32 1 iclk 0008 6428h mpu region-5 start page number register rspage5 32 32 1 iclk 0008 642ch mpu region-5 end page number register repage5 32 32 1 iclk 0008 6430h mpu region-6 start page number register rspage6 32 32 1 iclk 0008 6434h mpu region-6 end page number register repage6 32 32 1 iclk 0008 6438h mpu region-7 start page number register rspage7 32 32 1 iclk 0008 643ch mpu region-7 end page number register repage7 32 32 1 iclk 0008 6500h mpu memory-protection enable register mpen 32 32 1 iclk 0008 6504h mpu background access control register mpbac 32 32 1 iclk 0008 6508h mpu memory-protection error status-clearing register mpeclr 32 32 1 iclk 0008 650ch mpu memory-protection error status register mpests 32 32 1 iclk 0008 6514h mpu data memory-protection error address register mpdea 32 32 1 iclk 0008 6520h mpu region search address register mpsa 32 32 1 iclk 0008 6524h mpu region search operation register mpops 16 16 1 iclk 0008 6526h mpu region invalidation operation register mpopi 16 16 1 iclk 0008 6528h mpu instruction-hit region register mhiti 32 32 1 iclk 0008 652ch mpu data-hit region register mhitd 32 32 1 iclk table 4.1 list of i/o regist ers (address order) (3/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 58 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 7010h icu interrupt request register 016 ir016 8 8 2 iclk icub 0008 7015h icu interrupt request register 021 ir021 8 8 2 iclk 0008 7017h icu interrupt request register 023 ir023 8 8 2 iclk 0008 701bh icu interrupt request register 027 ir027 8 8 2 iclk 0008 701ch icu interrupt request register 028 ir028 8 8 2 iclk 0008 701dh icu interrupt request register 029 ir029 8 8 2 iclk 0008 701eh icu interrupt request register 030 ir030 8 8 2 iclk 0008 701fh icu interrupt request register 031 ir031 8 8 2 iclk 0008 7021h icu interrupt request register 033 ir033 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 7022h icu interrupt request register 034 ir034 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 7023h icu interrupt request register 035 ir035 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 7024h icu interrupt request register 036 ir036 8 8 2 iclk 0008 7025h icu interrupt request register 037 ir037 8 8 2 iclk 0008 7026h icu interrupt request register 038 ir038 8 8 2 iclk 0008 7027h icu interrupt request register 039 ir039 8 8 2 iclk 0008 7028h icu interrupt request register 040 ir040 8 8 2 iclk 0008 7029h icu interrupt request register 041 ir041 8 8 2 iclk 0008 702ah icu interrupt request register 042 ir042 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 702bh icu interrupt request register 043 ir043 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 702ch icu interrupt request register 044 ir044 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 702dh icu interrupt request register 045 ir045 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 702eh icu interrupt request register 046 ir046 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 702fh icu interrupt request register 047 ir047 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7030h icu interrupt request register 048 ir048 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7031h icu interrupt request register 049 ir049 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7032h icu interrupt request register 050 ir050 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7033h icu interrupt request register 051 ir051 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7034h icu interrupt request register 052 ir052 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7035h icu interrupt request register 053 ir053 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7036h icu interrupt request register 054 ir054 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7037h icu interrupt request register 055 ir055 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7038h icu interrupt request register 056 ir056 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7039h icu interrupt request register 057 ir057 8 8 2 iclk 0008 703ah icu interrupt request register 058 ir058 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 703bh icu interrupt request register 059 ir059 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 703ch icu interrupt request register 060 ir060 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 703dh icu interrupt request register 061 ir061 8 8 2 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o regist ers (address order) (4/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 59 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 703eh icu interrupt request register 062 ir062 8 8 2 iclk icub not present in versions with 64 or 48 pins. 0008 7040h icu interrupt request register 064 ir064 8 8 2 iclk 0008 7041h icu interrupt request register 065 ir065 8 8 2 iclk 0008 7042h icu interrupt request register 066 ir066 8 8 2 iclk 0008 7043h icu interrupt request register 067 ir067 8 8 2 iclk 0008 7044h icu interrupt request register 068 ir068 8 8 2 iclk 0008 7045h icu interrupt request register 069 ir069 8 8 2 iclk 0008 7046h icu interrupt request register 070 ir070 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7047h icu interrupt request register 071 ir071 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 705ah icu interrupt request register 090 ir090 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 7062h icu interrupt request register 098 ir098 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7066h icu interrupt request register 102 ir102 8 8 2 iclk 0008 7067h icu interrupt request register 103 ir103 8 8 2 iclk 0008 7068h icu interrupt request register 104 ir104 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7069h icu interrupt request register 105 ir105 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 706ah icu interrupt request register 106 ir106 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7072h icu interrupt request register 114 ir114 8 8 2 iclk 0008 707ah icu interrupt request register 122 ir122 8 8 2 iclk 0008 707bh icu interrupt request register 123 ir123 8 8 2 iclk 0008 707ch icu interrupt request register 124 ir124 8 8 2 iclk 0008 707dh icu interrupt request register 125 ir125 8 8 2 iclk 0008 707eh icu interrupt request register 126 ir126 8 8 2 iclk 0008 707fh icu interrupt request register 127 ir127 8 8 2 iclk 0008 7080h icu interrupt request register 128 ir128 8 8 2 iclk 0008 7081h icu interrupt request register 129 ir129 8 8 2 iclk 0008 7082h icu interrupt request register 130 ir130 8 8 2 iclk 0008 7083h icu interrupt request register 131 ir131 8 8 2 iclk 0008 7084h icu interrupt request register 132 ir132 8 8 2 iclk 0008 7085h icu interrupt request register 133 ir133 8 8 2 iclk 0008 7086h icu interrupt request register 134 ir134 8 8 2 iclk 0008 7087h icu interrupt request register 135 ir135 8 8 2 iclk 0008 7088h icu interrupt request register 136 ir136 8 8 2 iclk 0008 7089h icu interrupt request register 137 ir137 8 8 2 iclk 0008 708ah icu interrupt request register 138 ir138 8 8 2 iclk 0008 708bh icu interrupt request register 139 ir139 8 8 2 iclk 0008 708ch icu interrupt request register 140 ir140 8 8 2 iclk 0008 708dh icu interrupt request register 141 ir141 8 8 2 iclk 0008 708eh icu interrupt request register 142 ir142 8 8 2 iclk 0008 708fh icu interrupt request register 143 ir143 8 8 2 iclk 0008 7090h icu interrupt request register 144 ir144 8 8 2 iclk 0008 7091h icu interrupt request register 145 ir145 8 8 2 iclk 0008 7092h icu interrupt request register 146 ir146 8 8 2 iclk 0008 7093h icu interrupt request register 147 ir147 8 8 2 iclk 0008 7094h icu interrupt request register 148 ir148 8 8 2 iclk 0008 7095h icu interrupt request register 149 ir149 8 8 2 iclk 0008 7096h icu interrupt request register 150 ir150 8 8 2 iclk 0008 7097h icu interrupt request register 151 ir151 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (5/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 60 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 7098h icu interrupt request register 152 ir152 8 8 2 iclk icub 0008 7099h icu interrupt request register 153 ir153 8 8 2 iclk 0008 709ah icu interrupt request register 154 ir154 8 8 2 iclk 0008 709bh icu interrupt request register 155 ir155 8 8 2 iclk 0008 709ch icu interrupt request register 156 ir156 8 8 2 iclk 0008 709dh icu interrupt request register 157 ir157 8 8 2 iclk 0008 709eh icu interrupt request register 158 ir158 8 8 2 iclk 0008 70a1h icu interrupt request register 161 ir161 8 8 2 iclk 0008 70a2h icu interrupt request register 162 ir162 8 8 2 iclk 0008 70a3h icu interrupt request register 163 ir163 8 8 2 iclk 0008 70a4h icu interrupt request register 164 ir164 8 8 2 iclk 0008 70a5h icu interrupt request register 165 ir165 8 8 2 iclk 0008 70a6h icu interrupt request register 166 ir166 8 8 2 iclk 0008 70a7h icu interrupt request register 167 ir167 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70a8h icu interrupt request register 168 ir168 8 8 2 iclk 0008 70a9h icu interrupt request register 169 ir169 8 8 2 iclk 0008 70aah icu interrupt request register 170 ir170 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70abh icu interrupt request register 171 ir171 8 8 2 iclk 0008 70ach icu interrupt request register 172 ir172 8 8 2 iclk 0008 70adh icu interrupt request register 173 ir173 8 8 2 iclk 0008 70aeh icu interrupt request register 174 ir174 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70afh icu interrupt request register 175 ir175 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70b0h icu interrupt request register 176 ir176 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70b1h icu interrupt request register 177 ir177 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70b2h icu interrupt request register 178 ir178 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70b3h icu interrupt request register 179 ir179 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70b4h icu interrupt request register 180 ir180 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70b5h icu interrupt request register 181 ir181 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70b6h icu interrupt request register 182 ir182 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70b7h icu interrupt request register 183 ir183 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70b8h icu interrupt request register 184 ir184 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70b9h icu interrupt request register 185 ir185 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70bah icu interrupt request register 186 ir186 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70bbh icu interrupt request register 187 ir187 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70bch icu interrupt request register 188 ir188 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70bdh icu interrupt request register 189 ir189 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70beh icu interrupt request register 190 ir190 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 70bfh icu interrupt request register 191 ir191 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. table 4.1 list of i/o regist ers (address order) (6/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 61 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 70c0h icu interrupt request register 192 ir192 8 8 2 iclk icub not present in versions with 112, 100, 64 or 48 pins. 0008 70c1h icu interrupt request register 193 ir193 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 70c2h icu interrupt request register 194 ir194 8 8 2 iclk 0008 70c3h icu interrupt request register 195 ir195 8 8 2 iclk 0008 70c4h icu interrupt request register 196 ir196 8 8 2 iclk 0008 70c5h icu interrupt request register 197 ir197 8 8 2 iclk 0008 70c6h icu interrupt request register 198 ir198 8 8 2 iclk 0008 70c7h icu interrupt request register 199 ir199 8 8 2 iclk 0008 70c8h icu interrupt request register 200 ir200 8 8 2 iclk 0008 70c9h icu interrupt request register 201 ir201 8 8 2 iclk 0008 70d6h icu interrupt request register 214 ir214 8 8 2 iclk 0008 70d7h icu interrupt request register 215 ir215 8 8 2 iclk 0008 70d8h icu interrupt request register 216 ir216 8 8 2 iclk 0008 70d9h icu interrupt request register 217 ir217 8 8 2 iclk 0008 70dah icu interrupt request register 218 ir218 8 8 2 iclk 0008 70dbh icu interrupt request register 219 ir219 8 8 2 iclk 0008 70dch icu interrupt request register 220 ir220 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70ddh icu interrupt request register 221 ir221 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70deh icu interrupt request register 222 ir222 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 70dfh icu interrupt request register 223 ir223 8 8 2 iclk not present in versions with 100, 64 or 48 pins. 0008 70e0h icu interrupt request register 224 ir224 8 8 2 iclk not present in versions with 100, 64 or 48 pins. 0008 70e1h icu interrupt request register 225 ir225 8 8 2 iclk not present in versions with 100, 64 or 48 pins. 0008 70e2h icu interrupt request register 226 ir226 8 8 2 iclk 0008 70e3h icu interrupt request register 227 ir227 8 8 2 iclk 0008 70e4h icu interrupt request register 228 ir228 8 8 2 iclk 0008 70e5h icu interrupt request register 229 ir229 8 8 2 iclk 0008 70e6h icu interrupt request register 230 ir230 8 8 2 iclk 0008 70e7h icu interrupt request register 231 ir231 8 8 2 iclk 0008 70e8h icu interrupt request register 232 ir232 8 8 2 iclk 0008 70e9h icu interrupt request register 233 ir233 8 8 2 iclk 0008 70eah icu interrupt request register 234 ir234 8 8 2 iclk 0008 70ebh icu interrupt request register 235 ir235 8 8 2 iclk 0008 70ech icu interrupt request register 236 ir236 8 8 2 iclk 0008 70eeh icu interrupt request register 238 ir238 8 8 2 iclk 0008 70efh icu interrupt request register 239 ir239 8 8 2 iclk 0008 70f0h icu interrupt request register 240 ir240 8 8 2 iclk 0008 70f1h icu interrupt request register 241 ir241 8 8 2 iclk 0008 70f2h icu interrupt request register 242 ir242 8 8 2 iclk 0008 70f4h icu interrupt request register 244 ir244 8 8 2 iclk 0008 70f5h icu interrupt request register 245 ir245 8 8 2 iclk 0008 70f6h icu interrupt request register 246 ir246 8 8 2 iclk 0008 70f7h icu interrupt request register 247 ir247 8 8 2 iclk 0008 70f8h icu interrupt request register 248 ir248 8 8 2 iclk 0008 70fah icu interrupt request register 250 ir250 8 8 2 iclk 0008 70fbh icu interrupt request register 251 ir251 8 8 2 iclk 0008 70fch icu interrupt request register 252 ir252 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (7/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 62 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 711bh icu dtc activation enable register 027 dtcer027 8 8 2 iclk icub 0008 711ch icu dtc activation enable register 028 dtcer028 8 8 2 iclk 0008 711dh icu dtc activation enable register 029 dtcer029 8 8 2 iclk 0008 711eh icu dtc activation enable register 030 dtcer030 8 8 2 iclk 0008 711fh icu dtc activation enable register 031 dtcer031 8 8 2 iclk 0008 7121h icu dtc activation enable register 033 dtcer033 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 7122h icu dtc activation enable register 034 dtcer034 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 7127h icu dtc activation enable register 039 dtcer039 8 8 2 iclk 0008 7128h icu dtc activation enable register 040 dtcer040 8 8 2 iclk 0008 712ah icu dtc activation enable register 042 dtcer042 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 712bh icu dtc activation enable register 043 dtcer043 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7131h icu dtc activation enable register 049 dtcer049 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7132h icu dtc activation enable register 050 dtcer050 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7133h icu dtc activation enable register 051 dtcer051 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7134h icu dtc activation enable register 052 dtcer052 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7135h icu dtc activation enable register 053 dtcer053 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7136h icu dtc activation enable register 054 dtcer054 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7137h icu dtc activation enable register 055 dtcer055 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7138h icu dtc activation enable register 056 dtcer056 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 713ah icu dtc activation enable register 058 dtcer058 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 713bh icu dtc activation enable register 059 dtcer059 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 713ch icu dtc activation enable register 060 dtcer060 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 713dh icu dtc activation enable register 061 dtcer061 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 713eh icu dtc activation enable register 062 dtcer062 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7140h icu dtc activation enable register 064 dtcer064 8 8 2 iclk 0008 7141h icu dtc activation enable register 065 dtcer065 8 8 2 iclk 0008 7142h icu dtc activation enable register 066 dtcer066 8 8 2 iclk 0008 7143h icu dtc activation enable register 067 dtcer067 8 8 2 iclk 0008 7144h icu dtc activation enable register 068 dtcer068 8 8 2 iclk 0008 7145h icu dtc activation enable register 069 dtcer069 8 8 2 iclk 0008 7146h icu dtc activation enable register 070 dtcer070 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7147h icu dtc activation enable register 071 dtcer071 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7162h icu dtc activation enable register 098 dtcer098 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7166h icu dtc activation enable register 102 dtcer102 8 8 2 iclk 0008 7167h icu dtc activation enable register 103 dtcer103 8 8 2 iclk 0008 7168h icu dtc activation enable register 104 dtcer104 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7169h icu dtc activation enable register 105 dtcer105 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 717eh icu dtc activation enable register 126 dtcer126 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (8/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 63 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 717fh icu dtc activation enable register 127 dtcer127 8 8 2 iclk icub 0008 7180h icu dtc activation enable register 128 dtcer128 8 8 2 iclk 0008 7181h icu dtc activation enable register 129 dtcer129 8 8 2 iclk 0008 7185h icu dtc activation enable register 133 dtcer133 8 8 2 iclk 0008 7186h icu dtc activation enable register 134 dtcer134 8 8 2 iclk 0008 7189h icu dtc activation enable register 137 dtcer137 8 8 2 iclk 0008 718ah icu dtc activation enable register 138 dtcer138 8 8 2 iclk 0008 718dh icu dtc activation enable register 141 dtcer141 8 8 2 iclk 0008 718eh icu dtc activation enable register 142 dtcer142 8 8 2 iclk 0008 718fh icu dtc activation enable register 143 dtcer143 8 8 2 iclk 0008 7190h icu dtc activation enable register 144 dtcer144 8 8 2 iclk 0008 7192h icu dtc activation enable register 146 dtcer146 8 8 2 iclk 0008 7193h icu dtc activation enable register 147 dtcer147 8 8 2 iclk 0008 7194h icu dtc activation enable register 148 dtcer148 8 8 2 iclk 0008 7195h icu dtc activation enable register 149 dtcer149 8 8 2 iclk 0008 7196h icu dtc activation enable register 150 dtcer150 8 8 2 iclk 0008 7197h icu dtc activation enable register 151 dtcer151 8 8 2 iclk 0008 7198h icu dtc activation enable register 152 dtcer152 8 8 2 iclk 0008 7199h icu dtc activation enable register 153 dtcer153 8 8 2 iclk 0008 719ah icu dtc activation enable register 154 dtcer154 8 8 2 iclk 0008 719bh icu dtc activation enable register 155 dtcer155 8 8 2 iclk 0008 719ch icu dtc activation enable register 156 dtcer156 8 8 2 iclk 0008 719dh icu dtc activation enable register 157 dtcer157 8 8 2 iclk 0008 71a1h icu dtc activation enable register 161 dtcer161 8 8 2 iclk 0008 71a2h icu dtc activation enable register 162 dtcer162 8 8 2 iclk 0008 71a3h icu dtc activation enable register 163 dtcer163 8 8 2 iclk 0008 71a4h icu dtc activation enable register 164 dtcer164 8 8 2 iclk 0008 71a5h icu dtc activation enable register 165 dtcer165 8 8 2 iclk 0008 71abh icu dtc activation enable register 171 dtcer171 8 8 2 iclk 0008 71ach icu dtc activation enable register 172 dtcer172 8 8 2 iclk 0008 71adh icu dtc activation enable register 173 dtcer173 8 8 2 iclk 0008 71aeh icu dtc activation enable register 174 dtcer174 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71afh icu dtc activation enable register 175 dtcer175 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71b0h icu dtc activation enable register 176 dtcer176 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71b1h icu dtc activation enable register 177 dtcer177 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71b2h icu dtc activation enable register 178 dtcer178 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71b3h icu dtc activation enable register 179 dtcer179 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71b4h icu dtc activation enable register 180 dtcer180 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71b5h icu dtc activation enable register 181 dtcer181 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71b6h icu dtc activation enable register 182 dtcer182 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71b7h icu dtc activation enable register 183 dtcer183 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71b8h icu dtc activation enable register 184 dtcer184 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71b9h icu dtc activation enable register 185 dtcer185 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71bah icu dtc activation enable register 186 dtcer186 8 8 2 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o regist ers (address order) (9/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 64 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 71bbh icu dtc activation enable register 187 dtcer187 8 8 2 iclk icub not present in versions with 64 or 48 pins. 0008 71bch icu dtc activation enable register 188 dtcer188 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71bdh icu dtc activation enable register 189 dtcer189 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71bfh icu dtc activation enable register 191 dtcer191 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 71c0h icu dtc activation enable register 192 dtcer192 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 71c3h icu dtc activation enable register 195 dtcer195 8 8 2 iclk 0008 71c4h icu dtc activation enable register 196 dtcer196 8 8 2 iclk 0008 71c6h icu dtc activation enable register 198 dtcer198 8 8 2 iclk 0008 71c7h icu dtc activation enable register 199 dtcer199 8 8 2 iclk 0008 71c8h icu dtc activation enable register 200 dtcer200 8 8 2 iclk 0008 71c9h icu dtc activation enable register 201 dtcer201 8 8 2 iclk 0008 71d6h icu dtc activation enable register 214 dtcer214 8 8 2 iclk 0008 71d7h icu dtc activation enable register 215 dtcer215 8 8 2 iclk 0008 71d9h icu dtc activation enable register 217 dtcer217 8 8 2 iclk 0008 71dah icu dtc activation enable register 218 dtcer218 8 8 2 iclk 0008 71dch icu dtc activation enable register 220 dtcer220 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71ddh icu dtc activation enable register 221 dtcer221 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 71dfh icu dtc activation enable register 223 dtcer223 8 8 2 iclk not present in versions with 100, 64 or 48 pins. 0008 71e0h icu dtc activation enable register 224 dtcer224 8 8 2 iclk not present in versions with 100, 64 or 48 pins. 0008 71e2h icu dtc activation enable register 226 dtcer226 8 8 2 iclk 0008 71e3h icu dtc activation enable register 227 dtcer227 8 8 2 iclk 0008 71e4h icu dtc activation enable register 228 dtcer228 8 8 2 iclk 0008 71e5h icu dtc activation enable register 229 dtcer229 8 8 2 iclk 0008 71e6h icu dtc activation enable register 230 dtcer230 8 8 2 iclk 0008 71e7h icu dtc activation enable register 231 dtcer231 8 8 2 iclk 0008 71e8h icu dtc activation enable register 232 dtcer232 8 8 2 iclk 0008 71e9h icu dtc activation enable register 233 dtcer233 8 8 2 iclk 0008 71eah icu dtc activation enable register 234 dtcer234 8 8 2 iclk 0008 71ebh icu dtc activation enable register 235 dtcer235 8 8 2 iclk 0008 71ech icu dtc activation enable register 236 dtcer236 8 8 2 iclk 0008 71eeh icu dtc activation enable register 238 dtcer238 8 8 2 iclk 0008 71efh icu dtc activation enable register 239 dtcer239 8 8 2 iclk 0008 71f0h icu dtc activation enable register 240 dtcer240 8 8 2 iclk 0008 71f1h icu dtc activation enable register 241 dtcer241 8 8 2 iclk 0008 71f2h icu dtc activation enable register 242 dtcer242 8 8 2 iclk 0008 71f4h icu dtc activation enable register 244 dtcer244 8 8 2 iclk 0008 71f5h icu dtc activation enable register 245 dtcer245 8 8 2 iclk 0008 71f6h icu dtc activation enable register 246 dtcer246 8 8 2 iclk 0008 71f7h icu dtc activation enable register 247 dtcer247 8 8 2 iclk 0008 71f8h icu dtc activation enable register 248 dtcer248 8 8 2 iclk 0008 71fah icu dtc activation enable register 250 dtcer250 8 8 2 iclk 0008 71fbh icu dtc activation enable register 251 dtcer251 8 8 2 iclk 0008 7202h icu interrupt request enable register 02 ier02 8 8 2 iclk 0008 7203h icu interrupt request enable register 03 ier03 8 8 2 iclk 0008 7204h icu interrupt request enable register 04 ier04 8 8 2 iclk 0008 7205h icu interrupt request enable register 05 ier05 8 8 2 iclk table 4.1 list of i/o registers (address order) (10/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 65 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 7206h icu interrupt request enable register 06 ier06 8 8 2 iclk icub not present in versions with 64 or 48 pins. 0008 7207h icu interrupt request enable register 07 ier07 8 8 2 iclk 0008 7208h icu interrupt request enable register 08 ier08 8 8 2 iclk 0008 720bh icu interrupt request enable register 0b ier0b 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 720ch icu interrupt request enable register 0c ier0c 8 8 2 iclk 0008 720dh icu interrupt request enable register 0d ier0d 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 720eh icu interrupt request enable register 0e ier0e 8 8 2 iclk 0008 720fh icu interrupt request enable register 0f ier0f 8 8 2 iclk 0008 7210h icu interrupt request enable register 10 ier10 8 8 2 iclk 0008 7211h icu interrupt request enable register 11 ier11 8 8 2 iclk 0008 7212h icu interrupt request enable register 12 ier12 8 8 2 iclk 0008 7213h icu interrupt request enable register 13 ier13 8 8 2 iclk 0008 7214h icu interrupt request enable register 14 ier14 8 8 2 iclk 0008 7215h icu interrupt request enable register 15 ier15 8 8 2 iclk 0008 7216h icu interrupt request enable register 16 ier16 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7217h icu interrupt request enable register 17 ier17 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7218h icu interrupt request enable register 18 ier18 8 8 2 iclk 0008 7219h icu interrupt request enable register 19 ier19 8 8 2 iclk 0008 721ah icu interrupt request enable register 1a ier1a 8 8 2 iclk 0008 721bh icu interrupt request enable register 1b ier1b 8 8 2 iclk 0008 721ch icu interrupt request enable register 1c ier1c 8 8 2 iclk 0008 721dh icu interrupt request enable register 1d ier1d 8 8 2 iclk 0008 721eh icu interrupt request enable register 1e ier1e 8 8 2 iclk 0008 721fh icu interrupt request enable register 1f ier1f 8 8 2 iclk 0008 72e0h icu software interrupt activation register swintr 8 8 2 iclk 0008 72f0h icu fast interrupt set register fir 16 16 2 iclk 0008 7300h icu interrupt source priority register 000 ipr000 8 8 2 iclk 0008 7301h icu interrupt source priority register 001 ipr001 8 8 2 iclk 0008 7302h icu interrupt source priority register 002 ipr002 8 8 2 iclk 0008 7303h icu interrupt source priority register 003 ipr003 8 8 2 iclk 0008 7304h icu interrupt source priority register 004 ipr004 8 8 2 iclk 0008 7305h icu interrupt source priority register 005 ipr005 8 8 2 iclk 0008 7306h icu interrupt source priority register 006 ipr006 8 8 2 iclk 0008 7307h icu interrupt source priority register 007 ipr007 8 8 2 iclk 0008 7321h icu interrupt source priority register 033 ipr033 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 7322h icu interrupt source priority register 034 ipr034 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 7323h icu interrupt source priority register 035 ipr035 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 7324h icu interrupt source priority register 036 ipr036 8 8 2 iclk 0008 7327h icu interrupt source priority register 039 ipr039 8 8 2 iclk 0008 7328h icu interrupt source priority register 040 ipr040 8 8 2 iclk 0008 7329h icu interrupt source priority register 041 ipr041 8 8 2 iclk 0008 732ah icu interrupt source priority register 042 ipr042 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 732b icu interrupt source priority register 043 ipr043 8 8 2 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (11/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 66 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 732c icu interrupt source priority register 044 ipr044 8 8 2 iclk icub not present in versions with 64 or 48 pins. 0008 732dh icu interrupt source priority register 045 ipr045 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7331h icu interrupt source priority register 049 ipr049 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7334h icu interrupt source priority register 052 ipr052 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7336h icu interrupt source priority register 054 ipr054 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7337h icu interrupt source priority register 055 ipr055 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7338h icu interrupt source priority register 056 ipr056 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7339h icu interrupt source priority register 057 ipr057 8 8 2 iclk 0008 733ah icu interrupt source priority register 058 ipr058 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 733bh icu interrupt source priority register 059 ipr059 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 733ch icu interrupt source priority register 060 ipr060 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 733dh icu interrupt source priority register 061 ipr061 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 733eh icu interrupt source priority register 062 ipr062 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7340h icu interrupt source priority register 064 ipr064 8 8 2 iclk 0008 7341h icu interrupt source priority register 065 ipr065 8 8 2 iclk 0008 7342h icu interrupt source priority register 066 ipr066 8 8 2 iclk 0008 7343h icu interrupt source priority register 067 ipr067 8 8 2 iclk 0008 7344h icu interrupt source priority register 068 ipr068 8 8 2 iclk 0008 7345h icu interrupt source priority register 069 ipr069 8 8 2 iclk 0008 7346h icu interrupt source priority register 070 ipr070 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7347h icu interrupt source priority register 071 ipr071 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 735ah icu interrupt source priority register 090 ipr090 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 7362h icu interrupt source priority register 098 ipr098 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7366h icu interrupt source priority register 102 ipr102 8 8 2 iclk 0008 7367h icu interrupt source priority register 103 ipr103 8 8 2 iclk 0008 7368h icu interrupt source priority register 104 ipr104 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7369h icu interrupt source priority register 105 ipr105 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 736ah icu interrupt source priority register 106 ipr106 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 7372h icu interrupt source priority register 114 ipr114 8 8 2 iclk 0008 737ah icu interrupt source priority register 122 ipr122 8 8 2 iclk 0008 737eh icu interrupt source priority register 126 ipr126 8 8 2 iclk 0008 7382h icu interrupt source priority register 130 ipr130 8 8 2 iclk 0008 7385h icu interrupt source priority register 133 ipr133 8 8 2 iclk 0008 7387h icu interrupt source priority register 135 ipr135 8 8 2 iclk 0008 7389h icu interrupt source priority register 137 ipr137 8 8 2 iclk 0008 738bh icu interrupt source priority register 139 ipr139 8 8 2 iclk 0008 738dh icu interrupt source priority register 141 ipr141 8 8 2 iclk 0008 7391h icu interrupt source priority register 145 ipr145 8 8 2 iclk 0008 7392h icu interrupt source priority register 146 ipr146 8 8 2 iclk 0008 7396h icu interrupt source priority register 150 ipr150 8 8 2 iclk 0008 7397h icu interrupt source priority register 151 ipr151 8 8 2 iclk table 4.1 list of i/o registers (address order) (12/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 67 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 739ah icu interrupt source priority register 154 ipr154 8 8 2 iclk icub 0008 739eh icu interrupt source priority register 158 ipr158 8 8 2 iclk 0008 73a1h icu interrupt source priority register 161 ipr161 8 8 2 iclk 0008 73a3h icu interrupt source priority register 163 ipr163 8 8 2 iclk 0008 73a5h icu interrupt source priority register 165 ipr165 8 8 2 iclk 0008 73a6h icu interrupt source priority register 166 ipr166 8 8 2 iclk 0008 73abh icu interrupt source priority register 171 ipr171 8 8 2 iclk 0008 73ach icu interrupt source priority register 172 ipr172 8 8 2 iclk 0008 73adh icu interrupt source priority register 173 ipr173 8 8 2 iclk 0008 73aeh icu interrupt source priority register 174 ipr174 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 73b1h icu interrupt source priority register 177 ipr177 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 73b4h icu interrupt source priority register 180 ipr180 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 73b7h icu interrupt source priority register 183 ipr183 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 73b9h icu interrupt source priority register 185 ipr185 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 73bch icu interrupt source priority register 188 ipr188 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 73beh icu interrupt source priority register 190 ipr190 8 8 2 iclk not present in versions with 112, 100, 64 or 48 pins. 0008 73c2h icu interrupt source priority register 194 ipr194 8 8 2 iclk 0008 73c6h icu interrupt source priority register 198 ipr198 8 8 2 iclk 0008 73c7h icu interrupt source priority register 199 ipr199 8 8 2 iclk 0008 73c8h icu interrupt source priority register 200 ipr200 8 8 2 iclk 0008 73c9h icu interrupt source priority register 201 ipr201 8 8 2 iclk 0008 73d6h icu interrupt source priority register 214 ipr214 8 8 2 iclk 0008 73d9h icu interrupt source priority register 217 ipr217 8 8 2 iclk 0008 73dch icu interrupt source priority register 220 ipr220 8 8 2 iclk not present in versions with 64 or 48 pins. 0008 73dfh icu interrupt source priority register 223 ipr223 8 8 2 iclk not present in versions with 100, 64 or 48 pins. 0008 73e2h icu interrupt source priority register 226 ipr226 8 8 2 iclk 0008 73e5h icu interrupt source priority register 229 ipr229 8 8 2 iclk 0008 73e8h icu interrupt source priority register 232 ipr232 8 8 2 iclk 0008 73ebh icu interrupt source priority register 235 ipr235 8 8 2 iclk 0008 73eeh icu interrupt source priority register 238 ipr238 8 8 2 iclk 0008 73f1h icu interrupt source priority register 241 ipr241 8 8 2 iclk 0008 73f4h icu interrupt source priority register 244 ipr244 8 8 2 iclk 0008 73f7h icu interrupt source priority register 247 ipr247 8 8 2 iclk 0008 73fah icu interrupt source priority register 250 ipr250 8 8 2 iclk 0008 7400h icu dmac activation request select register 0 dmrsr0 8 8 2 iclk 0008 7404h icu dmac activation request select register 1 dmrsr1 8 8 2 iclk 0008 7408h icu dmac activation request select register 2 dmrsr2 8 8 2 iclk 0008 740ch icu dmac activation request select register 3 dmrsr3 8 8 2 iclk 0008 7500h icu irq control register 0 irqcr0 8 8 2 iclk 0008 7501h icu irq control register 1 irqcr1 8 8 2 iclk 0008 7502h icu irq control register 2 irqcr2 8 8 2 iclk 0008 7503h icu irq control register 3 irqcr3 8 8 2 iclk 0008 7504h icu irq control register 4 irqcr4 8 8 2 iclk 0008 7505h icu irq control register 5 irqcr5 8 8 2 iclk 0008 7506h icu irq control register 6 irqcr6 8 8 2 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (13/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 68 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 7507h icu irq control register 7 irqcr7 8 8 2 iclk icub not present in versions with 64 or 48 pins. 0008 7510h icu irq pin digital filter enable register 0 irqflte0 8 8 2 iclk 0008 7514h icu irq pin digital filter setting register 0 irqfltc0 16 16 2 iclk 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2 iclk 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2 iclk 0008 7582h icu non-maskable interrupt status clear register nmiclr 8 8 2 iclk 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2 iclk 0008 7590h icu nmi pin digital filter enable register nmiflte 8 8 2 iclk 0008 7594h icu nmi pin digital filter setting register nmifltc 8 8 2 iclk 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2, 3 pclkb 2 iclk cmt 0008 8002h cmt0 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 8004h cmt0 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 8006h cmt0 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8008h cmt1 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 800ah cmt1 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 800ch cmt1 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8010h cmt compare match timer start register 1 cmstr1 16 16 2, 3 pclkb 2 iclk 0008 8012h cmt2 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 8014h cmt2 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 8016h cmt2 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8018h cmt3 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 801ah cmt3 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 801ch cmt3 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8020h wdt wdt refresh register wdtrr 8 8 2, 3 pclkb 2 iclk wdta 0008 8022h wdt wdt control register wdtcr 16 16 2, 3 pclkb 2 iclk 0008 8024h wdt wdt status register wdtsr 16 16 2, 3 pclkb 2 iclk 0008 8026h wdt wdt reset control register wdtrcr 8 8 2, 3 pclkb 2 iclk 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2, 3 pclkb 2 iclk iwdta 0008 8032h iwdt iwdt control register iwdtcr 16 16 2, 3 pclkb 2 iclk 0008 8034h iwdt iwdt status register iwdtsr 16 16 2, 3 pclkb 2 iclk 0008 8036h iwdt iwdt reset control register iwdtrcr 8 8 2, 3 pclkb 2 iclk 0008 8038h iwdt iwdt count stop control register iwdtcstpr 8 8 2, 3 pclkb 2 iclk 0008 80c0h da d/a data register 0 dadr0 16 16 2, 3 pclkb 2 iclk daa not present in versions with 64 or 48 pins. 0008 80c2h da d/a data register 1 dadr1 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 80c4h da d/a control register dacr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 80c5h da dadrm format select register dadpr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 80c6h da d/a a/d synchronous start control register daadscr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 8280h crc crc control register crccr 8 8 2, 3 pclkb 2 iclk crc 0008 8281h crc crc data input register crcdir 8 8 2, 3 pclkb 2 iclk 0008 8282h crc crc data output register crcdor 16 16 2, 3 pclkb 2 iclk 0008 8300h riic0 i 2 c bus control register 1 iccr1 8 8 2, 3 pclkb 2 iclk riic 0008 8301h riic0 i 2 c bus control register 2 iccr2 8 8 2, 3 pclkb 2 iclk 0008 8302h riic0 i 2 c bus mode register 1 icmr1 8 8 2, 3 pclkb 2 iclk 0008 8303h riic0 i 2 c bus mode register 2 icmr2 8 8 2, 3 pclkb 2 iclk 0008 8304h riic0 i 2 c bus mode register 3 icmr3 8 8 2, 3 pclkb 2 iclk 0008 8305h riic0 i 2 c bus function enable register icfer 8 8 2, 3 pclkb 2 iclk 0008 8306h riic0 i 2 c bus status enable register icser 8 8 2, 3 pclkb 2 iclk 0008 8307h riic0 i 2 c bus interrupt enable register icier 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o registers (address order) (14/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 69 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 8308h riic0 i 2 c bus status register 1 icsr1 8 8 2, 3 pclkb 2 iclk riic 0008 8309h riic0 i 2 c bus status register 2 icsr2 8 8 2, 3 pclkb 2 iclk 0008 830ah riic0 slave address register l0 sarl0 8 8 2, 3 pclkb 2 iclk 0008 830ah riic0 timeout internal counter l tmocntl 8 8 2, 3 pclkb 2 iclk 0008 830bh riic0 slave address register u0 saru0 8 8 2, 3 pclkb 2 iclk 0008 830bh riic0 timeout internal counter u tmocntu 8 8* 2 2, 3 pclkb 2 iclk 0008 830ch riic0 slave address register l1 sarl1 8 8 2, 3 pclkb 2 iclk 0008 830dh riic0 slave address register u1 saru1 8 8 2, 3 pclkb 2 iclk 0008 830eh riic0 slave address register l2 sarl2 8 8 2, 3 pclkb 2 iclk 0008 830fh riic0 slave address register u2 saru2 8 8 2, 3 pclkb 2 iclk 0008 8310h riic0 i 2 c bus bit rate low-level register icbrl 8 8 2, 3 pclkb 2 iclk 0008 8311h riic0 i 2 c bus bit rate high-level register icbrh 8 8 2, 3 pclkb 2 iclk 0008 8312h riic0 i 2 c bus transmit data register icdrt 8 8 2, 3 pclkb 2 iclk 0008 8313h riic0 i 2 c bus receive data register icdrr 8 8 2, 3 pclkb 2 iclk 0008 8320h riic1 i 2 c bus control register 1 iccr1 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 8321h riic1 i 2 c bus control register 2 iccr2 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 8322h riic1 i 2 c bus mode register 1 icmr1 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 8323h riic1 i 2 c bus mode register 2 icmr2 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 8324h riic1 i 2 c bus mode register 3 icmr3 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 8325h riic1 i 2 c bus function enable register icfer 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 8326h riic1 i 2 c bus status enable register icser 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 8327h riic1 i 2 c bus interrupt enable register icier 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 8328h riic1 i 2 c bus status register 1 icsr1 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 8329h riic1 i 2 c bus status register 2 icsr2 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 832ah riic1 slave address register l0 sarl0 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 832ah riic1 timeout internal counter l tmocntl 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 832bh riic1 slave address register u0 saru0 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 832bh riic1 timeout internal counter u tmocntu 8 8* 2 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 832ch riic1 slave address register l1 sarl1 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 832dh riic1 slave address register u1 saru1 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 832eh riic1 slave address register l2 sarl2 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 832fh riic1 slave address register u2 saru2 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. table 4.1 list of i/o registers (address order) (15/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 70 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 8330h riic1 i 2 c bus bit rate low-level register icbrl 8 8 2, 3 pclkb 2 iclk riic not present in versions with 112, 100, 64, or 48 pins. 0008 8331h riic1 i 2 c bus bit rate high-level register icbrh 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 8332h riic1 i 2 c bus transmit data register icdrt 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 8333h riic1 i 2 c bus receive data register icdrr 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 8380h rspi0 rspi control register spcr 8 8 2, 3 pclkb 2 iclk rspi 0008 8381h rspi0 rspi slave select polarity register sslp 8 8 2, 3 pclkb 2 iclk 0008 8382h rspi0 rspi pin control register sppcr 8 8 2, 3 pclkb 2 iclk 0008 8383h rspi0 rspi status register spsr 8 8 2, 3 pclkb 2 iclk 0008 8384h rspi0 rspi data register spdr 32 16, 32 2, 3 pclkb 2 iclk 0008 8388h rspi0 rspi sequence control register spscr 8 8 2, 3 pclkb 2 iclk 0008 8389h rspi0 rspi sequence status register spssr 8 8 2, 3 pclkb 2 iclk 0008 838ah rspi0 rspi bit rate register spbr 8 8 2, 3 pclkb 2 iclk 0008 838bh rspi0 rspi data control register spdcr 8 8 2, 3 pclkb 2 iclk 0008 838ch rspi0 rspi clock delay register spckd 8 8 2, 3 pclkb 2 iclk 0008 838dh rspi0 rspi slave select negation delay register sslnd 8 8 2, 3 pclkb 2 iclk 0008 838eh rspi0 rspi next-access delay register spnd 8 8 2, 3 pclkb 2 iclk 0008 838fh rspi0 rspi control register 2 spcr2 8 8 2, 3 pclkb 2 iclk 0008 8390h rspi0 rspi command register 0 spcmd0 16 16 2, 3 pclkb 2 iclk 0008 8392h rspi0 rspi command register 1 spcmd1 16 16 2, 3 pclkb 2 iclk 0008 8394h rspi0 rspi command register 2 spcmd2 16 16 2, 3 pclkb 2 iclk 0008 8396h rspi0 rspi command register 3 spcmd3 16 16 2, 3 pclkb 2 iclk 0008 8398h rspi0 rspi command register 4 spcmd4 16 16 2, 3 pclkb 2 iclk 0008 839ah rspi0 rspi command register 5 spcmd5 16 16 2, 3 pclkb 2 iclk 0008 839ch rspi0 rspi command register 6 spcmd6 16 16 2, 3 pclkb 2 iclk 0008 839eh rspi0 rspi command register 7 spcmd7 16 16 2, 3 pclkb 2 iclk 0008 83a0h rspi1 rspi control register spcr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83a1h rspi1 rspi slave select polarity register sslp 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83a2h rspi1 rspi pin control register sppcr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83a3h rspi1 rspi status register spsr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83a4h rspi1 rspi data register spdr 32 16, 32 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83a8h rspi1 rspi sequence control register spscr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83a9h rspi1 rspi sequence status register spssr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83aah rspi1 rspi bit rate register spbr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83abh rspi1 rspi data control register spdcr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83ach rspi1 rspi clock delay register spckd 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83adh rspi1 rspi slave select negation delay register sslnd 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83aeh rspi1 rspi next-access delay register spnd 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83afh rspi1 rspi control register 2 spcr2 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83b0h rspi1 rspi command register 0 spcmd0 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (16/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 71 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 83b2h rspi1 rspi command register 1 spcmd1 16 16 2, 3 pclkb 2 iclk rspi not present in versions with 64 or 48 pins. 0008 83b4h rspi1 rspi command register 2 spcmd2 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83b6h rspi1 rspi command register 3 spcmd3 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83b8h rspi1 rspi command register 4 spcmd4 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83bah rspi1 rspi command register 5 spcmd5 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83bch rspi1 rspi command register 6 spcmd6 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 83beh rspi1 rspi command register 7 spcmd7 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9000h s12ad a/d control register adcsr 16 16 2, 3 pclkb 2 iclk s12adb 0008 9004h s12ad a/d channel select register a adansa 16 16 2, 3 pclkb 2 iclk 0008 9008h s12ad a/d-converted value addition mode select register adads 16 16 2, 3 pclkb 2 iclk 0008 900ch s12ad a/d-converted value addition count select register adadc 8 8 2, 3 pclkb 2 iclk 0008 900eh s12ad a/d control extended register adcer 16 16 2, 3 pclkb 2 iclk 0008 9010h s12ad a/d start trigger select register adstrgr 16 16 2, 3 pclkb 2 iclk 0008 9014h s12ad a/d channel select register b adansb 16 16 2, 3 pclkb 2 iclk 0008 9018h s12ad a/d data-doubling register addbldr 16 16 2, 3 pclkb 2 iclk 0008 901eh s12ad a/d self-diagnosis data register adrd 16 16 2, 3 pclkb 2 iclk 0008 9020h s12ad a/d data register 0 addr0 16 16 2, 3 pclkb 2 iclk 0008 9022h s12ad a/d data register 1 addr1 16 16 2, 3 pclkb 2 iclk 0008 9024h s12ad a/d data register 2 addr2 16 16 2, 3 pclkb 2 iclk 0008 9026h s12ad a/d data register 3 addr3 16 16 2, 3 pclkb 2 iclk 0008 9028h s12ad a/d data register 4 addr4 16 16 2, 3 pclkb 2 iclk not present in versions with 144, 120, 112, or 100 pins. 0008 902ah s12ad a/d data register 5 addr5 16 16 2, 3 pclkb 2 iclk not present in versions with 144, 120, 112, or 100 pins. 0008 902ch s12ad a/d data register 6 addr6 16 16 2, 3 pclkb 2 iclk not present in versions with 144, 120, 112, or 100 pins. 0008 902eh s12ad a/d data register 7 addr7 16 16 2, 3 pclkb 2 iclk not present in versions with 144, 120, 112, or 100 pins. 0008 9060h s12ad a/d sampling state register 0 adsstr0 8 8 2, 3 pclkb 2 iclk 0008 9066h s12ad a/d sample and hold circuit control register adshcr 16 16 2, 3 pclkb 2 iclk 0008 9073h s12ad a/d sampling state register 1 adsstr1 8 8 2, 3 pclkb 2 iclk 0008 9074h s12ad a/d sampling state register 2 adsstr2 8 8 2, 3 pclkb 2 iclk 0008 9075h s12ad a/d sampling state register 3 adsstr3 8 8 2, 3 pclkb 2 iclk 0008 9076h s12ad a/d sampling state register 4 adsstr4 8 8 2, 3 pclkb 2 iclk not present in versions with 144, 120, 112, or 100 pins. 0008 9077h s12ad a/d sampling state register 5 adsstr5 8 8 2, 3 pclkb 2 iclk not present in versions with 144, 120, 112, or 100 pins. 0008 9078h s12ad a/d sampling state register 6 adsstr6 8 8 2, 3 pclkb 2 iclk not present in versions with 144, 120, 112, or 100 pins. 0008 9079h s12ad a/d sampling state register 7 adsstr7 8 8 2, 3 pclkb 2 iclk not present in versions with 144, 120, 112, or 100 pins. 0008 9080h s12ad a/d group scan priority control register adgspcr 16 16 2, 3 pclkb 2 iclk 0008 9084h s12ad a/d data-doubling register a addbldra 16 16 2, 3 pclkb 2 iclk 0008 9086h s12ad a/d data-doubling register b addbldrb 16 16 2, 3 pclkb 2 iclk 0008 908ah s12ad a/d programmable gain amplifier register adpg 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (17/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 72 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 90e0h s12ad comparator operating mode selection register 0 adcmpmd0 16 16 2, 3 pclkb 2 iclk s12adb 0008 90e2h s12ad comparator operating-mode selection register 1 adcmpmd1 16 16 2, 3 pclkb 2 iclk 0008 90e4h s12ad comparator filter-mode register adcmpnr0 16 16 2, 3 pclkb 2 iclk 0008 90e8h s12ad comparator detection flag register adcmpfr 8 8 2, 3 pclkb 2 iclk 0008 90eah s12ad comparator interrupt selection register adcmpsel 16 16 2, 3 pclkb 2 iclk 0008 90fch s12ad a/d group scan priority control register adgspmr 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9100h s12ad1 a/d control register adcsr 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9104h s12ad1 a/d channel select register a adansa 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9108h s12ad1 a/d-converted value addition mode select register (adads) adads 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 910ch s12ad1 a/d-converted value addition count select register adadc 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 910eh s12ad1 a/d control extended register adcer 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9110h s12ad1 a/d start trigger select register adstrgr 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9114h s12ad1 a/d channel select register b adansb 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9118h s12ad1 a/d data-doubling register addbldr 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 911eh s12ad1 a/d self-diagnosis data register adrd 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9120h s12ad1 a/d data register 0 addr0 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9122h s12ad1 a/d data register 1 addr1 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9124h s12ad1 a/d data register 2 addr2 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9126h s12ad1 a/d data register 3 addr3 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9160h s12ad1 a/d sampling state register 0 adsstr0 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9166h s12ad1 a/d sample and hold circuit control register adshcr 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9173h s12ad1 a/d sampling state register 1 adsstr1 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9174h s12ad1 a/d sampling state register 2 adsstr2 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9175h s12ad1 a/d sampling state register 3 adsstr3 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9180h s12ad1 a/d group scan priority control register adgspcr 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9184h s12ad1 a/d data-doubling register a addbldra 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9186h s12ad1 a/d data-doubling register b addbldrb 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 918ah s12ad1 a/d programmable gain amplifier register adpg 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 91e0h s12ad1 comparator operating mode selection register 0 adcmpmd0 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 91e2h s12ad1 comparator operating-mode selection register 1 adcmpmd1 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 91e4h s12ad1 comparator filter-mode register adcmpnr0 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 91e8h s12ad1 comparator detection flag register adcmpfr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 91eah s12ad1 comparator interrupt selection register adcmpsel 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9800h ad a/d control register adcsr 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (18/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 73 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 9804h ad a/d channel select register 0 adansa0 16 16 2, 3 pclkb 2 iclk ad not present in versions with 64 or 48 pins. 0008 9806h ad a/d channel select register 1 adansa1 16 16 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64 or 48 pins. 0008 9808h ad a/d-converted value addition mode select register0 adads0 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 980ah ad a/d-converted value addition mode select register1 adads1 16 16 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64 or 48 pins. 0008 980ch ad a/d-converted value addition count select register adadc 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 980eh ad a/d control extended register adcer 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9810h ad a/d start trigger select register adstrgr 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 981eh ad a/d self-diagnosis data register adrd 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9820h ad a/d data register a addra 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9822h ad a/d data register b addrb 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9824h ad a/d data register c addrc 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9826h ad a/d data register d addrd 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9828h ad a/d data register e addre 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 982ah ad a/d data register f addrf 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 982ch ad a/d data register g addrg 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 982eh ad a/d data register h addrh 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9830h ad a/d data register i addri 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9832h ad a/d data register j addrj 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9834h ad a/d data register k addrk 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9836h ad a/d data register l addrl 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9838h ad a/d data register m addrm 16 16 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 983ah ad a/d data register n addrn 16 16 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 983ch ad a/d data register o addro 16 16 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 983eh ad a/d data register p addrp 16 16 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 9840h ad a/d data register q addrq 16 16 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 9842h ad a/d data register r addrr 16 16 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 9844h ad a/d data register s addrs 16 16 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 9846h ad a/d data register t addrt 16 16 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 9860h ad a/d sampling state register 0 adsstr0 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9861h ad a/d sampling state register l adsstrl 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (19/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 74 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 9873h ad a/d sampling state register 1 adsstr1 8 8 2, 3 pclkb 2 iclk ad not present in versions with 64 or 48 pins. 0008 9874h ad a/d sampling state register 2 adsstr2 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9875h ad a/d sampling state register 3 adsstr3 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9876h ad a/d sampling state register 4 adsstr4 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9877h ad a/d sampling state register 5 adsstr5 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9878h ad a/d sampling state register 6 adsstr6 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 9879h ad a/d sampling state register 7 adsstr7 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 987dh ad digital power supply control circuit output register addpconr 8 8 2, 3 pclkb 2 iclk not present in versions with 64, or 48 pins. 0008 a000h sci0 serial mode register smr 8 8 2, 3 pclkb 2 iclk scic, scid 0008 a001h sci0 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a002h sci0 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a003h sci0 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a004h sci0 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a005h sci0 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a006h sci0 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a007h sci0 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a008h sci0 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a009h sci0 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a00ah sci0 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a00bh sci0 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a00ch sci0 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a00dh sci0 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a020h sci1 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a021h sci1 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a022h sci1 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a023h sci1 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a024h sci1 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a025h sci1 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a026h sci1 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a027h sci1 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a028h sci1 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a029h sci1 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a02ah sci1 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a02bh sci1 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a02ch sci1 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a02dh sci1 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a040h sci2 serial mode register smr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 a041h sci2 bit rate register brr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 a042h sci2 serial control register scr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 a043h sci2 transmit data register tdr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 a044h sci2 serial status register ssr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 a045h sci2 receive data register rdr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 a046h sci2 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (20/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 75 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 a047h sci2 serial extended mode register semr 8 8 2 , 3 pclkb 2 iclk scic, scid not present in versions with 64 or 48 pins. 0008 a048h sci2 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 a049h sci2 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 a04ah sci2 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 a04bh sci2 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 a04ch sci2 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 a04dh sci2 spi mode register spmr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 a060h sci3 serial mode register smr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a061h sci3 bit rate register brr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a062h sci3 serial control register scr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a063h sci3 transmit data register tdr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a064h sci3 serial status register ssr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a065h sci3 receive data register rdr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a066h sci3 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a067h sci3 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a068h sci3 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a069h sci3 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a06ah sci3 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a06bh sci3 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a06ch sci3 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 a06dh sci3 spi mode register spmr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 b000h cac cac control register 0 cacr0 8 8 2, 3 pclkb 2 iclk cac 0008 b001h cac cac control register 1 cacr1 8 8 2, 3 pclkb 2 iclk 0008 b002h cac cac control register 2) cacr2 8 8 2, 3 pclkb 2 iclk 0008 b003h cac cac interrupt control register caicr 8 8 2, 3 pclkb 2 iclk 0008 b004h cac cac status register castr 8 8 2, 3 pclkb 2 iclk 0008 b006h cac cac upper-limit value setting register caulvr 16 16 2, 3 pclkb 2 iclk 0008 b008h cac cac lower-limit value setting register callvr 16 16 2, 3 pclkb 2 iclk 0008 b00ah cac cac counter buffer register cacntbr 16 16 2, 3 pclkb 2 iclk 0008 b080h doc doc control register docr 8 8 2, 3 pclkb 2 iclk doc 0008 b082h doc doc data input register dodir 16 16 2, 3 pclkb 2 iclk 0008 b084h doc doc data setting register dodsr 16 16 2, 3 pclkb 2 iclk 0008 b300h sci12 serial mode register smr 8 8 2, 3 pclkb 2 iclk scic, scid 0008 b301h sci12 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 b302h sci12 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 b303h sci12 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 b304h sci12 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 b305h sci12 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 b306h sci12 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 b307h sci12 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o registers (address order) (21/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 76 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 b308h sci12 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk scic, scid 0008 b309h sci12 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 b30ah sci12 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 b30bh sci12 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 b30ch sci12 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 b30dh sci12 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 b320h sci12 extended serial module enable register esmer 8 8 2, 3 pclkb 2 iclk 0008 b321h sci12 control register 0 cr0 8 8 2, 3 pclkb 2 iclk 0008 b322h sci12 control register 1 cr1 8 8 2, 3 pclkb 2 iclk 0008 b323h sci12 control register 2 cr2 8 8 2, 3 pclkb 2 iclk 0008 b324h sci12 control register 3 cr3 8 8 2, 3 pclkb 2 iclk 0008 b325h sci12 port control register pcr 8 8 2, 3 pclkb 2 iclk 0008 b326h sci12 interrupt control register icr 8 8 2, 3 pclkb 2 iclk 0008 b327h sci12 status register str 8 8 2, 3 pclkb 2 iclk 0008 b328h sci12 status clear register stcr 8 8 2, 3 pclkb 2 iclk 0008 b329h sci12 control field 0 data register cf0dr 8 8 2, 3 pclkb 2 iclk 0008 b32ah sci12 control field 0 compare enable register cf0cr 8 8 2, 3 pclkb 2 iclk 0008 b32bh sci12 control field 0 receive data register cf0rr 8 8 2, 3 pclkb 2 iclk 0008 b32ch sci12 primary control field 1 data register pcf1dr 8 8 2, 3 pclkb 2 iclk 0008 b32dh sci12 primary control field 1 data register scf1dr 8 8 2, 3 pclkb 2 iclk 0008 b32eh sci12 secondary control field 1 data register cf1cr 8 8 2, 3 pclkb 2 iclk 0008 b32fh sci12 control field 1 receive data register cf1rr 8 8 2, 3 pclkb 2 iclk 0008 b330h sci12 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 b331h sci12 timer mode register tmr 8 8 2, 3 pclkb 2 iclk 0008 b332h sci12 timer prescaler register tpre 8 8 2, 3 pclkb 2 iclk 0008 b333h sci12 timer count register tcnt 8 8 2, 3 pclkb 2 iclk 0008 c000h port0 port direction register pdr 8 8 2, 3 pclkb 2 iclk i/o ports not present in versions with 48 pins. 0008 c001h port1 port direction register pdr 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c002h port2 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c003h port3 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c007h port7 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c008h port8 port direction register pdr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c009h port9 port direction register pdr 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c00ah porta port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00bh portb port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00dh portd port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00eh porte port direction register pdr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c00fh portf port direction register pdr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c010h portg port direction register pdr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c020h port0 port output data register podr 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c021h port1 port output data register podr 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c022h port2 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c023h port3 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c027h port7 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c028h port8 port output data register podr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c029h port9 port output data register podr 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. table 4.1 list of i/o registers (address order) (22/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 77 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 c02ah porta port output data register podr 8 8 2, 3 pclkb 2 iclk i/o ports 0008 c02bh portb port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02dh portd port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02eh porte port output data register podr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c02fh portf port output data register podr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c030h portg port output data register podr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c040h port0 port input data register pidr 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c041h port1 port input data register pidr 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c042h port2 port input data register pidr 8 8 2, 3 pclkb 2 iclk 0008 c043h port3 port input data register pidr 8 8 2, 3 pclkb 2 iclk 0008 c044h port4 port input data register pidr 8 8 2, 3 pclkb 2 iclk 0008 c045h port5 port input data register pidr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c046h port6 port input data register pidr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c047h port7 port input data register pidr 8 8 2, 3 pclkb 2 iclk 0008 c048h port8 port input data register pidr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c049h port9 port input data register pidr 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c04ah porta port input data register pidr 8 8 2, 3 pclkb 2 iclk 0008 c04bh portb port input data register pidr 8 8 2, 3 pclkb 2 iclk 0008 c04ch portc port input data register pidr 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c04dh portd port input data register pidr 8 8 2, 3 pclkb 2 iclk 0008 c04eh porte port input data register pidr 8 8 2, 3 pclkb 2 iclk 0008 c04fh portf port input data register pidr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c050h portg port input data register pidr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c060h port0 port mode register pmr 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c061h port1 port mode register pmr 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c062h port2 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c063h port3 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c067h port7 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c068h port8 port mode register pmr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c069h port9 port mode register pmr 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c06ah porta port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06bh portb port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06dh portd port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06eh porte port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06fh portf port mode register pmr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c070h portg port mode register pmr 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c080h port0 open drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64 or 48 pins. 0008 c084h port2 open drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c085h port2 open drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk not present in versions with 112 or 100 pins. table 4.1 list of i/o registers (address order) (23/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 78 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 c086h port3 open drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk i/o ports not present in versions with 144, 120, 112, or 100 pins. 0008 c087h port3 open drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64 or 48 pins. 0008 c090h port8 open drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c092h port9 open drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk not present in versions with 144, 120, 112, 100 or 48 pins. 0008 c093h port9 open drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c094h porta open drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c095h porta open drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c096h portb open drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk 0008 c097h portb open drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk 0008 c09ah portd open drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk 0008 c09bh portd open drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk 0008 c09eh portf open drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c0a0h portg open drain control register 0 odr0 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c0a1h portg open drain control register 1 odr1 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c0f2h port driving ability control register 1 d scr1 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c0f3h port driving ability control register 2 dscr2 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c100h mpc cs output enable register pfcse 8 8 2, 3 pclkb 2 iclk mpc not present in versions with 64 or 48 pins. 0008 c102h mpc cs output pin select register 0 pfcss0 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c104h mpc address output enable register 0 pfaoe0 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c105h mpc address output enable register 1 pfaoe1 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c106h mpc external bus control register 0 pfbcr0 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c107h mpc external bus control register 1 pfbcr1 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c114h mpc usb0 control register pfusb0 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 c11fh mpc write-protect register pwpr 8 8 2, 3 pclkb 2 iclk 0008 c140h mpc p00 pin function control register p00pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c141h mpc p01 pin function control register p01pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c142h mpc p02 pin function control register p02pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c143h mpc p03 pin function control register p03pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c148h mpc p10 pin function control register p10pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c149h mpc p11 pin function control register p11pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c14ah mpc p12 pin function control register p12pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c14bh mpc p13 pin function control register p13pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. table 4.1 list of i/o registers (address order) (24/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 79 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 c14ch mpc p14 pin function control register p14pfs 8 8 2, 3 pclkb 2 iclk mpc not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c150h mpc p20 pin function control register p20pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c151h mpc p21 pin function control register p21pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c152h mpc p22 pin function control register p22pfs 8 8 2, 3 pclkb 2 iclk 0008 c153h mpc p23 pin function control register p23pfs 8 8 2, 3 pclkb 2 iclk 0008 c154h mpc p24 pin function control register p24pfs 8 8 2, 3 pclkb 2 iclk 0008 c155h mpc p25 pin function control register p25pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 c156h mpc p26 pin function control register p26pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 c158h mpc p30 pin function control register p30pfs 8 8 2, 3 pclkb 2 iclk 0008 c159h mpc p31 pin function control register p31pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c15ah mpc p32 pin function control register p32pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c15bh mpc p33 pin function control register p33pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c15ch mpc p34 pin function control register p34pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c15dh mpc p35 pin function control register p35pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c160h mpc p40 pin function control register p40pfs 8 8 2, 3 pclkb 2 iclk 0008 c161h mpc p41 pin function control register p41pfs 8 8 2, 3 pclkb 2 iclk 0008 c162h mpc p42 pin function control register p42pfs 8 8 2, 3 pclkb 2 iclk 0008 c163h mpc p43 pin function control register p43pfs 8 8 2, 3 pclkb 2 iclk 0008 c164h mpc p44 pin function control register p44pfs 8 8 2, 3 pclkb 2 iclk 0008 c165h mpc p45 pin function control register p45pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c166h mpc p46 pin function control register p46pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c167h mpc p47 pin function control register p47pfs 8 8 2, 3 pclkb 2 iclk 0008 c168h mpc p50 pin function control register p50pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c169h mpc p51 pin function control register p51pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c16ah mpc p52 pin function control register p52pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c16bh mpc p53 pin function control register p53pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c16ch mpc p54 pin function control register p54pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c16dh mpc p55 pin function control register p55pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c16eh mpc p56 pin function control register p56pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c16fh mpc p57 pin function control register p57pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c170h mpc p60 pin function control register p60pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c171h mpc p61 pin function control register p61pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c172h mpc p62 pin function control register p62pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c173h mpc p63 pin function control register p63pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (25/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 80 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 c174h mpc p64 pin function control register p64pfs 8 8 2, 3 pclkb 2 iclk mpc not present in versions with 64 or 48 pins. 0008 c175h mpc p65 pin function control register p65pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c178h mpc p70 pin function control register p70pfs 8 8 2, 3 pclkb 2 iclk 0008 c179h mpc p71 pin function control register p71pfs 8 8 2, 3 pclkb 2 iclk 0008 c17ah mpc p72 pin function control register p72pfs 8 8 2, 3 pclkb 2 iclk 0008 c17bh mpc p73 pin function control register p73pfs 8 8 2, 3 pclkb 2 iclk 0008 c17ch mpc p74 pin function control register p74pfs 8 8 2, 3 pclkb 2 iclk 0008 c17dh mpc p75 pin function control register p75pfs 8 8 2, 3 pclkb 2 iclk 0008 c17eh mpc p76 pin function control register p76pfs 8 8 2, 3 pclkb 2 iclk 0008 c180h mpc p80 pin function control register p80pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c181h mpc p81 pin function control register p81pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c182h mpc p82 pin function control register p82pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c188h mpc p90 pin function control register p90pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c189h mpc p91 pin function control register p91pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c18ah mpc p92 pin function control register p92pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c18bh mpc p93 pin function control register p93pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c18ch mpc p94 pin function control register p94pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c18dh mpc p95 pin function control register p95pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c18eh mpc p96 pin function control register p96pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c190h mpc pa0 pin function control register pa0pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c191h mpc pa1 pin function control register pa1pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c192h mpc pa2 pin function control register pa2pfs 8 8 2, 3 pclkb 2 iclk 0008 c193h mpc pa3 pin function control register pa3pfs 8 8 2, 3 pclkb 2 iclk 0008 c194h mpc pa4 pin function control register pa4pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c195h mpc pa5 pin function control register pa5pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c196h mpc pa6 pin function control register pa6pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64 or 48 pins. 0008 c198h mpc pb0 pin function control register pb0pfs 8 8 2, 3 pclkb 2 iclk 0008 c199h mpc pb1 pin function control register pb1pfs 8 8 2, 3 pclkb 2 iclk 0008 c19ah mpc pb2 pin function control register pb2pfs 8 8 2, 3 pclkb 2 iclk 0008 c19bh mpc pb3 pin function control register pb3pfs 8 8 2, 3 pclkb 2 iclk 0008 c19ch mpc pb4 pin function control register pb4pfs 8 8 2, 3 pclkb 2 iclk 0008 c19dh mpc pb5 pin function control register pb5pfs 8 8 2, 3 pclkb 2 iclk 0008 c19eh mpc pb6 pin function control register pb6pfs 8 8 2, 3 pclkb 2 iclk 0008 c19fh mpc pb7 pin function control register pb7pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 48 pins. 0008 c1a0h mpc pc0 pin function control register pc0pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c1a1h mpc pc1 pin function control register pc1pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c1a2h mpc pc2 pin function control register pc2pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. table 4.1 list of i/o registers (address order) (26/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 81 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 c1a3h mpc pc3 pin function control register pc3pfs 8 8 2, 3 pclkb 2 iclk mpc not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c1a4h mpc pc4 pin function control register pc4pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c1a5h mpc pc5 pin function control register pc5pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 120, 112, 100, 64, or 48 pins. 0008 c1a8h mpc pd0 pin function control register pd0pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c1a9h mpc pd1 pin function control register pd1pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c1aah mpc pd2 pin function control register pd2pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c1abh mpc pd3 pin function control register pd3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1ach mpc pd4 pin function control register pd4pfs 8 8 2, 3 pclkb 2 iclk 0008 c1adh mpc pd5 pin function control register pd5pfs 8 8 2, 3 pclkb 2 iclk 0008 c1aeh mpc pd6 pin function control register pd6pfs 8 8 2, 3 pclkb 2 iclk 0008 c1afh mpc pd7 pin function control register pd7pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b0h mpc pe0 pin function control register pe0pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c1b1h mpc pe1 pin function control register pe1pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c1b2h mpc pe2 pin function control register pe2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b3h mpc pe3 pin function control register pe3pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c1b4h mpc pe4 pin function control register pe4pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c1b5h mpc pe5 pin function control register pe5pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c1bah mpc pf2 pin function control register pf2pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c1bbh mpc pf3 pin function control register pf3pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c1c0h mpc pg0 pin function control register pg0pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c1c1h mpc pg1 pin function control register pg1pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c1c2h mpc pg2 pin function control register pg2pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c1c3h mpc pg3 pin function control register pg3pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c1c4h mpc pg4 pin function control register pg4pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c1c5h mpc pg5 pin function control register pg5pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 100, 64, or 48 pins. 0008 c1c6h mpc pg6 pin function control register pg6pfs 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 c1d0h mpc usb0_dpupe pin func tion control register udpupepfs 8 8 2, 3 pclkb 2 iclk not present in versions with 112, 100, 64, or 48 pins. 0008 c280h system deep standby control register dpsbycr 8 8 4, 5 pclkb 2, 3 iclk low power consumption 0008 c282h system deep standby interrupt enable register 0 dpsier0 8 8 4, 5 pclkb 2, 3 iclk 0008 c284h system deep standby interrupt enable register 2 dpsier2 8 8 4, 5 pclkb 2, 3 iclk 0008 c286h system deep standby interrupt flag register 0 dpsifr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c288h system deep standby interrupt flag register 2 dpsifr2 8 8 4, 5 pclkb 2, 3 iclk 0008 c28ah system deep standby interrupt edge register 0 dpsiegr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c28ch system deep standby interrupt edge register 2 dpsiegr2 8 8 4, 5 pclkb 2, 3 iclk 0008 c290h system reset status register 0 rstsr0 8 8 4, 5 pclkb 2, 3 iclk resets 0008 c291h system reset status register 1 rstsr1 8 8 4, 5 pclkb 2, 3 iclk table 4.1 list of i/o registers (address order) (27/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 82 of 186 mar 31, 2016 rx63t group 4. i/o registers 0008 c293h system main clock oscillator forced oscillation control register mofcr 8 8 4, 5 pclkb 2, 3 iclk clock generation circuit 0008 c296h flash flash p/e protection register fwepror 8 8 4, 5 pclkb 2, 3 iclk rom 0008 c297h system voltage monitoring circuit control register lvcmpcr 8 8 4, 5 pclkb 2, 3 iclk lvda 0008 c298h system voltage detection level select register lvdlvlr 8 8 4, 5 pclkb 2, 3 iclk 0008 c29ah system voltage monitoring 1 circuit control register 0 lvd1cr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c29bh system voltage monitoring 2 circuit control register 0 lvd2cr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c2a0h to 0008 c2bfh system deep standby backup register 0 to 31 dpsbkr0 to 31 8 8 4, 5 pclkb 2, 3 iclk low power consumption 0008 c300h icu group 0 interrupt source register grp00 32 32 1, 2 pclkb 2 iclk icub not present in versions with 64 or 48 pins. 0008 c330h icu group 12 interrupt source register grp12 32 32 1, 2 pclkb 2 iclk 0008 c340h icu group 0 interrupt enable register gen00 32 32 1, 2 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c370h icu group 12 interrupt enable register gen12 32 32 1, 2 pclkb 2 iclk 0008 c380h icu group 0 interrupt clear register gcr00 32 32 1, 2 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c4c0h poe input level control/status register 1 icsr1 16 8, 16 2, 3 pclkb 2 iclk poe3 0008 c4c2h poe output level control/status register 1 ocsr1 16 8, 16 2, 3 pclkb 2 iclk 0008 c4c4h poe input level control/status register 2 icsr2 16 8, 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c4c6h poe output level control/status register 2 ocsr2 16 8, 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c4c8h poe input level control/status register 3 icsr3 16 8, 16 2, 3 pclkb 2 iclk 0008 c4cah poe software port output enable register spoer 8 8 2, 3 pclkb 2 iclk 0008 c4cbh poe port output enable control register 1 poecr1 8 8 2, 3 pclkb 2 iclk 0008 c4cch poe port output enable control register 2 poecr2 16 16 2, 3 pclkb 2 iclk 0008 c4ceh poe port output enable control register 3 poecr3 16 16 2, 3 pclkb 2 iclk 0008 c4d0h poe port output enable control register 4 poecr4 16 16 2, 3 pclkb 2 iclk 0008 c4d2h poe port output enable control register 5 poecr5 16 16 2, 3 pclkb 2 iclk 0008 c4d4h poe port output enable control register 6 poecr6 16 16 2, 3 pclkb 2 iclk 0008 c4d6h poe input level control/status register 4 icsr4 16 8, 16 2, 3 pclkb 2 iclk 0008 c4d8h poe input level control/status register 5 icsr5 16 8, 16 2, 3 pclkb 2 iclk 0008 c4dah poe active level setting register 1 alr1 16 8, 16 2, 3 pclkb 2 iclk 0008 c4dch poe input level control/status register 6 icsr6 16 16 2, 3 pclkb 2 iclk 0008 c4deh poe active level setting register 2 alr2 16 8, 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c4e0h poe input level control/status register 7 icsr7 16 8, 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c4e2h poe port output enable control register 7 poecr7 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0008 c4e4h poe port output enable control register 8 poecr8 16 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1200h to 0009 13ffh can1 mailbox register 0 to 31 mb0 to 31 128 8, 16, 32 2, 3 pclkb 2 iclk can not present in versions with 64 or 48 pins. 0009 1400h to 0009 141ch can1 mask register 0 to 7 mkr0 to 7 32 8, 16, 32 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1420h can1 fifo received id compare register 0 and 1 fidcr0 32 8, 16, 32 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1424h can1 fifo received id compare register 0 and 1 fidcr1 32 8, 16, 32 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1428h can1 mask invalid register mkivlr 32 8, 16, 32 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 142ch can1 mailbox interrupt enable register mier 32 8, 16, 32 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1820h to 0009 183fh can1 message control register 0 to 31 mctl0 to 31 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (28/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 83 of 186 mar 31, 2016 rx63t group 4. i/o registers 0009 1840h can1 control register ctlr 16 8, 16 2, 3 pclkb 2 iclk can not present in versions with 64 or 48 pins. 0009 1842h can1 status register str 16 8, 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1844h can1 bit configuration register bcr 32 8, 16, 32 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1848h can1 receive fifo control register rfcr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1849h can1 receive fifo pointer control register rfpcr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 184ah can1 transmit fifo control register tfcr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 184bh can1 transmit fifo pointer control register tfpcr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 184ch can1 error interrupt enable register eier 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 184dh can1 error interrupt factor judge register eifr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 184eh can1 receive error count register recr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 184fh can1 transmit error count register tecr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1850h can1 error code store register ecsr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1851h can1 channel search support register cssr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1852h can1 mailbox search status register mssr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1853h can1 mailbox search mode register msmr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1854h can1 time stamp register tsr 16 8, 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1856h can1 acceptance filter support register afsr 16 8, 16 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 0009 1858h can1 test control register tcr 8 8 2, 3 pclkb 2 iclk not present in versions with 64 or 48 pins. 000a 0000h usb0 system configuration control register syscfg 16 16 3, 4 pclkb 2, 3 iclk usba not present in versions with 112, 100, 64, or 48 pins. 000a 0004h usb0 system configuration status register 0 syssts0 16 16 9 pclkb or more not present in versions with 112, 100, 64, or 48 pins. 000a 0008h usb0 device state control register 0 dvstctr0 16 16 9 pclkb or more not present in versions with 112, 100, 64, or 48 pins. 000a 0014h usb0 cfifo port register cfifo 16 8, 16 3, 4 pclkb 2, 3 iclk not present in versions with 112, 100, 64, or 48 pins. 000a 0018h usb0 d0fifo port registe d0fifo 16 8, 16 3, 4 pclkb 2, 3 iclk not present in versions with 112, 100, 64, or 48 pins. 000a 001ch usb0 d1fifo port register d1fifo 16 8, 16 3, 4 pclkb 2, 3 iclk not present in versions with 112, 100, 64, or 48 pins. 000a 0020h usb0 cfifo port select register cfifosel 16 16 3, 4 pclkb 2, 3 iclk not present in versions with 112, 100, 64, or 48 pins. 000a 0022h usb0 cfifo port control register cfifoctr 16 16 3, 4 pclkb 2, 3 iclk not present in versions with 112, 100, 64, or 48 pins. 000a 0028h usb0 d0fifo port select register d0fifosel 16 16 3, 4 pclkb 2, 3 iclk not present in versions with 112, 100, 64, or 48 pins. 000a 002ah usb0 d0fifo port control register d0fifoctr 16 16 3, 4 pclkb 2, 3 iclk not present in versions with 112, 100, 64, or 48 pins. 000a 002ch usb0 d1fifo port select regist er d1fifosel 16 16 3, 4 pclkb 2, 3 iclk not present in versions with 112, 100, 64, or 48 pins. table 4.1 list of i/o registers (address order) (29/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 84 of 186 mar 31, 2016 rx63t group 4. i/o registers 000a 002eh usb0 d1fifo port control register d1fifoctr 16 16 3, 4 pclkb 2, 3 iclk usba not present in versions with 112, 100, 64, or 48 pins. 000a 0030h usb0 interrupt enable register 0 intenb0 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0032h usb0 interrupt enable register 1 intenb1 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0036h usb0 brdy interrupt enable register brdyenb 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0038h usb0 nrdy interrupt enable register nrdyenb 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 003ah usb0 bemp interrupt enable register bempenb 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 003ch usb0 sof output configuration register sofcfg 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0040h usb0 interrupt status register 0 intsts0 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0042h usb0 interrupt status register 1 intsts1 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0046h usb0 brdy interrupt status register brdysts 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0048h usb0 nrdy interrupt status register nrdysts 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 004ah usb0 bemp interrupt status register bempsts 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. table 4.1 list of i/o registers (address order) (30/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 85 of 186 mar 31, 2016 rx63t group 4. i/o registers 000a 004ch usb0 frame number register frmnum 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 usba not present in versions with 112, 100, 64, or 48 pins. 000a 004eh usb0 device state change register dvchgr 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0050h usb0 usb address register usbaddr 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0054h usb0 usb request type register usbreq 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0056h usb0 usb request value register usbval 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0058h usb0 usb request index register usbindx 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 005ah usb0 usb request length register usbleng 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 005ch usb0 dcp configuration register dcpcfg 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 005eh usb0 dcp maximum packet size register dcpmaxp 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0060h usb0 dcp control register dcpctr 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0064h usb0 pipe window select register pipesel 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0068h usb0 pipe configuration register pipecfg 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. table 4.1 list of i/o registers (address order) (31/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 86 of 186 mar 31, 2016 rx63t group 4. i/o registers 000a 006ch usb0 pipe maximum packet size register pipemaxp 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 usba not present in versions with 112, 100, 64, or 48 pins. 000a 006eh usb0 pipe cycle control register pipeperi 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0070h usb0 pipe1 control register pipe1ctr 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0072h usb0 pipe2 control register pipe2ctr 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0074h usb0 pipe3 control register pipe3ctr 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0076h usb0 pipe4 control register pipe4ctr 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0078h usb0 pipe5 control register pipe5ctr 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 007ah usb0 pipe6 control register pipe6ctr 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 007ch usb0 pipe7 control register pipe7ctr 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 007eh usb0 pipe8 control register pipe8ctr 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0080h usb0 pipe9 control register pipe9ctr 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0090h usb0 pipe1 transaction counter enable register pipe1tre 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. table 4.1 list of i/o registers (address order) (32/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 87 of 186 mar 31, 2016 rx63t group 4. i/o registers 000a 0092h usb0 pipe1 transaction counter register pipe1trn 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 usba not present in versions with 112, 100, 64, or 48 pins. 000a 0094h usb0 pipe2 transaction counter enable register pipe2tre 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0096h usb0 pipe2 transaction counter register pipe2trn 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 0098h usb0 pipe3 transaction counter enable register pipe3tre 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 009ah usb0 pipe3 transaction counter register pipe3trn 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 009ch usb0 pipe4 transaction counter enable register pipe4tre 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 009eh usb0 pipe4 transaction counter register pipe4trn 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 00a0h usb0 pipe5 transaction counter enable register pipe5tre 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000a 00a2h usb0 pipe5 transaction counter register pipe5trn 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of iclk/ pclkb)* 1 not present in versions with 112, 100, 64, or 48 pins. 000c 1200h mtu3 timer control register tcr 8 8, 16, 32 4, 5 pclka 2, 3 iclk mtu3 000c 1201h mtu4 timer control register tcr 8 8 4, 5 pclka 2, 3 iclk 000c 1202h mtu3 timer mode register 1 tmdr1 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1203h mtu4 timer mode register 1 tmdr1 8 8 4, 5 pclka 2, 3 iclk 000c 1204h mtu3 timer i/o control register h tiorh 8 8, 16, 32 4, 5 pclka 2, 3 iclk 000c 1205h mtu3 timer i/o control register l tiorl 8 8 4, 5 pclka 2, 3 iclk 000c 1206h mtu4 timer i/o control register h tiorh 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1207h mtu4 timer i/o control register l tiorl 8 8 4, 5 pclka 2, 3 iclk 000c 1208h mtu3 timer interrupt enable register tier 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1209h mtu4 timer interrupt enable register tier 8 8 4, 5 pclka 2, 3 iclk 000c 120ah mtu timer output master enable register a toera 8 8 4, 5 pclka 2, 3 iclk 000c 120dh mtu timer gate control register a tgcra 8 8 4, 5 pclka 2, 3 iclk 000c 120eh mtu timer output control register 1a tocr1a 8 8, 16 4, 5 pclka 2, 3 iclk table 4.1 list of i/o registers (address order) (33/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 88 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 120fh mtu timer output control register 2a tocr2a 8 8 4, 5 pclka 2, 3 iclk mtu3 000c 1210h mtu3 timer counter tcnt 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1212h mtu4 timer counter tcnt 16 16 4, 5 pclka 2, 3 iclk 000c 1214h mtu timer cycle data register a tcdra 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1216h mtu timer dead time data register a tddra 16 16 4, 5 pclka 2, 3 iclk 000c 1218h mtu3 timer general register a tgra 16 16, 32 4, 5 pclka 2, 3 iclk 000c 121ah mtu3 timer general register b tgrb 16 16 4, 5 pclka 2, 3 iclk 000c 121ch mtu4 timer general register a tgra 16 16, 32 4, 5 pclka 2, 3 iclk 000c 121eh mtu4 timer general register b tgrb 16 16 4, 5 pclka 2, 3 iclk 000c 1220h mtu timer subcounter a tcntsa 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1222h mtu timer cycle buffer register a tcbra 16 16 4, 5 pclka 2, 3 iclk 000c 1224h mtu3 timer general register c tgrc 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1226h mtu3 timer general register d tgrd 16 16 4, 5 pclka 2, 3 iclk 000c 1228h mtu4 timer general register c tgrc 16 16, 32 4, 5 pclka 2, 3 iclk 000c 122ah mtu4 timer general register d tgrd 16 16 4, 5 pclka 2, 3 iclk 000c 122ch mtu3 timer status register tsr 8 8, 16 4, 5 pclka 2, 3 iclk 000c 122dh mtu4 timer status register tsr 8 8 4, 5 pclka 2, 3 iclk 000c 1230h mtu timer interrupt skipping set register 1a titcr1a 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1231h mtu timer interrupt skipping counters 1a titcnt1a 8 8 4, 5 pclka 2, 3 iclk 000c 1232h mtu timer buffer transfer set register a tbtera 8 8 4, 5 pclka 2, 3 iclk 000c 1234h mtu timer dead time enable register a tdera 8 8 4, 5 pclka 2, 3 iclk 000c 1236h mtu timer output level buffer register a tolbra 8 8 4, 5 pclka 2, 3 iclk 000c 1238h mtu3 timer buffer operation transfer mode register tbtm 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1239h mtu4 timer buffer operation transfer mode register tbtm 8 8 4, 5 pclka 2, 3 iclk 000c 123ah mtu timer interrupt skipping mode register a titmra 8 8 4, 5 pclka 2, 3 iclk 000c 123bh mtu timer interrupt skipping set register 2a titcr2a 8 8 4, 5 pclka 2, 3 iclk 000c 123ch mtu timer interrupt skipping counters 2a titcnt2a 8 8 4, 5 pclka 2, 3 iclk 000c 1240h mtu4 timer a/d converter start request control register tadcr 16 16 4, 5 pclka 2, 3 iclk 000c 1244h mtu4 timer a/d converter start request cycle set register a tadcora 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1246h mtu4 timer a/d converter start request cycle set register b tadcorb 16 16 4, 5 pclka 2, 3 iclk 000c 1248h mtu4 timer a/d converter start request cycle set buffer register a tadcobra 16 16, 32 4, 5 pclka 2, 3 iclk 000c 124ah mtu4 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 4, 5 pclka 2, 3 iclk 000c 1260h mtu timer waveform control register a twcra 8 8 4, 5 pclka 2, 3 iclk 000c 1270h mtu timer mode register 2a tmdr2a 8 8 4, 5 pclka 2, 3 iclk 000c 1272h mtu3 timer general register e tgre 16 16 4, 5 pclka 2, 3 iclk 000c 1274h mtu4 timer general register e tgre 16 16 4, 5 pclka 2, 3 iclk 000c 1276h mtu4 timer general register f tgrf 16 16 4, 5 pclka 2, 3 iclk 000c 1280h mtu timer start register a tstra 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1281h mtu timer synchronous register a tsyra 8 8 4, 5 pclka 2, 3 iclk 000c 1282h mtu timer counter synchronous start register tcsystr 8 8 4, 5 pclka 2, 3 iclk 000c 1284h mtu timer read/write enable register a trwera 8 8 4, 5 pclka 2, 3 iclk 000c 1300h mtu0 timer control register tcr 8 8, 16, 32 4, 5 pclka 2, 3 iclk 000c 1301h mtu0 timer mode register 1 tmdr1 8 8 4, 5 pclka 2, 3 iclk 000c 1302h mtu0 timer i/o control register h tiorh 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1303h mtu0 timer i/o control register l tiorl 8 8 4, 5 pclka 2, 3 iclk 000c 1304h mtu0 timer interrupt enable register tier 8 8, 16, 32 4, 5 pclka 2, 3 iclk 000c 1305h mtu0 timer status register tsr 8 8 4, 5 pclka 2, 3 iclk 000c 1306h mtu0 timer counter tcnt 16 16 4, 5 pclka 2, 3 iclk table 4.1 list of i/o registers (address order) (34/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 89 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 1308h mtu0 timer general register a tgra 16 16, 32 4, 5 pclka 2, 3 iclk mtu3 000c 130ah mtu0 timer general register b tgrb 16 16 4, 5 pclka 2, 3 iclk 000c 130ch mtu0 timer general register c tgrc 16 16, 32 4, 5 pclka 2, 3 iclk 000c 130eh mtu0 timer general register d tgrd 16 16 4, 5 pclka 2, 3 iclk 000c 1320h mtu0 timer general register e tgre 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1322h mtu0 timer general register f tgrf 16 16 4, 5 pclka 2, 3 iclk 000c 1324h mtu0 timer interrupt enable register 2 tier2 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1325h mtu0 timer status register 2 tsr2 8 8 4, 5 pclka 2, 3 iclk 000c 1326h mtu0 timer buffer operation transfer mode register tbtm 8 8 4, 5 pclka 2, 3 iclk 000c 1380h mtu1 timer control register tcr 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1381h mtu1 timer mode register 1 tmdr1 8 8 4, 5 pclka 2, 3 iclk 000c 1382h mtu1 timer i/o control register tior 8 8 4, 5 pclka 2, 3 iclk 000c 1384h mtu1 timer interrupt enable register tier 8 8, 16, 32 4, 5 pclka 2, 3 iclk 000c 1385h mtu1 timer status register tsr 8 8 4, 5 pclka 2, 3 iclk 000c 1386h mtu1 timer counter tcnt 16 16 4, 5 pclka 2, 3 iclk 000c 1388h mtu1 timer general register a tgra 16 16, 32 4, 5 pclka 2, 3 iclk 000c 138ah mtu1 timer general register b tgrb 16 16 4, 5 pclka 2, 3 iclk 000c 1390h mtu1 timer input capture control register ticcr 8 8 4, 5 pclka 2, 3 iclk 000c 1400h mtu2 timer control register tcr 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1401h mtu2 timer mode register 1 tmdr1 8 8 4, 5 pclka 2, 3 iclk 000c 1402h mtu2 timer i/o control register tior 8 8 4, 5 pclka 2, 3 iclk 000c 1404h mtu2 timer interrupt enable register tier 8 8, 16, 32 4, 5 pclka 2, 3 iclk 000c 1405h mtu2 timer status register tsr 8 8 4, 5 pclka 2, 3 iclk 000c 1406h mtu2 timer counter tcnt 16 16 4, 5 pclka 2, 3 iclk 000c 1408h mtu2 timer general register a tgra 16 16, 32 4, 5 pclka 2, 3 iclk 000c 140ah mtu2 timer general register b tgrb 16 16 4, 5 pclka 2, 3 iclk 000c 1a00h mtu6 timer control register tcr 8 8, 16, 32 4, 5 pclka 2, 3 iclk 000c 1a01h mtu7 timer control register tcr 8 8 4, 5 pclka 2, 3 iclk 000c 1a02h mtu6 timer mode register 1 tmdr1 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1a03h mtu7 timer mode register 1 tmdr1 8 8 4, 5 pclka 2, 3 iclk 000c 1a04h mtu6 timer i/o control register h tiorh 8 8, 16, 32 4, 5 pclka 2, 3 iclk 000c 1a05h mtu6 timer i/o control register l tiorl 8 8 4, 5 pclka 2, 3 iclk 000c 1a06h mtu7 timer i/o control register h tiorh 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1a07h mtu7 timer i/o control register l tiorl 8 8 4, 5 pclka 2, 3 iclk 000c 1a08h mtu6 timer interrupt enable register tier 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1a09h mtu7 timer interrupt enable register tier 8 8 4, 5 pclka 2, 3 iclk 000c 1a0ah mtu timer output master enable register b toerb 8 8 4, 5 pclka 2, 3 iclk 000c 1a0eh mtu timer output control register 1b tocr1b 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1a0fh mtu timer output control register 2b tocr2b 8 8 4, 5 pclka 2, 3 iclk 000c 1a10h mtu6 timer counter tcnt 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1a12h mtu7 timer counter tcnt 16 16 4, 5 pclka 2, 3 iclk 000c 1a14h mtu timer cycle data register b tcdrb 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1a16h mtu timer dead time data register b tddrb 16 16 4, 5 pclka 2, 3 iclk 000c 1a18h mtu6 timer general register a tgra 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1a1ah mtu6 timer general register b tgrb 16 16 4, 5 pclka 2, 3 iclk 000c 1a1ch mtu7 timer general register a tgra 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1a1eh mtu7 timer general register b tgrb 16 16 4, 5 pclka 2, 3 iclk 000c 1a20h mtu timer subcounter b tcntsb 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1a22h mtu timer cycle buffer register b tcbrb 16 16 4, 5 pclka 2, 3 iclk 000c 1a24h mtu6 timer general register c tgrc 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1a26h mtu6 timer general register d tgrd 16 16 4, 5 pclka 2, 3 iclk table 4.1 list of i/o registers (address order) (35/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 90 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 1a28h mtu7 timer general register c tgrc 16 16, 32 4, 5 pclka 2, 3 iclk mtu3 000c 1a2ah mtu7 timer general register d tgrd 16 16 4, 5 pclka 2, 3 iclk 000c 1a2ch mtu6 timer status register tsr 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1a2dh mtu7 timer status register tsr 8 8 4, 5 pclka 2, 3 iclk 000c 1a30h mtu timer interrupt skipping set register 1b titcr1b 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1a31h mtu timer interrupt skipping counters 1b titcnt1b 8 8 4, 5 pclka 2, 3 iclk 000c 1a32h mtu timer buffer transfer set register b tbterb 8 8 4, 5 pclka 2, 3 iclk 000c 1a34h mtu timer dead time enable register b tderb 8 8 4, 5 pclka 2, 3 iclk 000c 1a36h mtu timer output level buffer register b tolbrb 8 8 4, 5 pclka 2, 3 iclk 000c 1a38h mtu6 timer buffer operation transfer mode register tbtm 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1a39h mtu7 timer buffer operation transfer mode register tbtm 8 8 4, 5 pclka 2, 3 iclk 000c 1a3ah mtu timer interrupt skipping mode register b titmrb 8 8 4, 5 pclka 2, 3 iclk 000c 1a3bh mtu timer interrupt skipping set register 2b titcr2b 8 8 4, 5 pclka 2, 3 iclk 000c 1a3ch mtu timer interrupt skipping counters 2b titcnt2b 8 8 4, 5 pclka 2, 3 iclk 000c 1a40h mtu7 timer a/d converter start request control register tadcr 16 16 4, 5 pclka 2, 3 iclk 000c 1a44h mtu7 timer a/d converter start request cycle set register a tadcora 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1a46h mtu7 timer a/d converter start request cycle set register b tadcorb 16 16 4, 5 pclka 2, 3 iclk 000c 1a48h mtu7 timer a/d converter start request cycle set buffer register a tadcobra 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1a4ah mtu7 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 4, 5 pclka 2, 3 iclk 000c 1a50h mtu timer synchronous clear register tsycr 8 8 4, 5 pclka 2, 3 iclk 000c 1a60h mtu timer waveform control register b twcrb 8 8 4, 5 pclka 2, 3 iclk 000c 1a70h mtu timer mode register 2b tmdr2b 8 8 4, 5 pclka 2, 3 iclk 000c 1a72h mtu6 timer general register e tgre 16 16 4, 5 pclka 2, 3 iclk 000c 1a74h mtu7 timer general register e tgre 16 16 4, 5 pclka 2, 3 iclk 000c 1a76h mtu7 timer general register f tgrf 16 16 4, 5 pclka 2, 3 iclk 000c 1a80h mtu timer start register b tstrb 8 8, 16 4, 5 pclka 2, 3 iclk 000c 1a81h mtu timer synchronous register b tsyrb 8 8 4, 5 pclka 2, 3 iclk 000c 1a84h mtu timer read/write enable register b trwerb 8 8 4, 5 pclka 2, 3 iclk 000c 1c80h mtu5 timer counter u tcntu 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1c82h mtu5 timer general register u tgru 16 16 4, 5 pclka 2, 3 iclk 000c 1c84h mtu5 timer control register u tcru 8 8 4, 5 pclka 2, 3 iclk 000c 1c86h mtu5 timer i/o control register u tioru 8 8 4, 5 pclka 2, 3 iclk 000c 1c90h mtu5 timer counter v tcntv 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1c92h mtu5 timer general register v tgrv 16 16 4, 5 pclka 2, 3 iclk 000c 1c94h mtu5 timer control register v tcrv 8 8 4, 5 pclka 2, 3 iclk 000c 1c96h mtu5 timer i/o control register v tiorv 8 8 4, 5 pclka 2, 3 iclk 000c 1ca0h mtu5 timer counter w tcntw 16 16, 32 4, 5 pclka 2, 3 iclk 000c 1ca2h mtu5 timer general register w tgrw 16 16 4, 5 pclka 2, 3 iclk 000c 1ca4h mtu5 timer control register w tcrw 8 8 4, 5 pclka 2, 3 iclk 000c 1ca6h mtu5 timer i/o control register w tiorw 8 8 4, 5 pclka 2, 3 iclk 000c 1cb0h mtu5 timer status register tsr 8 8 4, 5 pclka 2, 3 iclk 000c 1cb2h mtu5 timer interrupt enable register tier 8 8 4, 5 pclka 2, 3 iclk 000c 1cb4h mtu5 timer start register tstr 8 8 4, 5 pclka 2, 3 iclk 000c 1cb6h mtu5 timer compare match clear register tcntcmpc lr 8 8 4, 5 pclka 2, 3 iclk 000c 2000h gpt general pwm timer software start register gtstr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk gpt 000c 2004h gpt general pwm timer hardware source start control register gthscr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk table 4.1 list of i/o registers (address order) (36/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 91 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 2006h gpt general pwm timer hardware source clear control register gthccr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk gpt 000c 2008h gpt general pwm timer hardware start source select register gthssr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 200ah gpt general pwm timer hardware stop/clear source select register gthpsr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 200ch gpt general pwm timer write-protection register gtwp 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 200eh gpt general pwm timer sync register gtsync 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2010h gpt general pwm timer external trigger input interrupt register gtetint 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2014h gpt general pwm timer buffer operation disable register gtbdr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2018h gpt general pwm timer start write-protection register gtswp 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2080h gpt loco count control register lccr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2082h gpt loco count status register lcst 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2084h gpt loco count value register lcnt 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2086h gpt loco count result average register lcnta 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2088h gpt loco count result register 0 lcnt00 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 208ah gpt loco count result register 1 lcnt01 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 208ch gpt loco count result register 2 lcnt02 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 208eh gpt loco count result register 3 lcnt03 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2090h gpt loco count result register 4 lcnt04 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2092h gpt loco count result register 5 lcnt05 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2094h gpt loco count result register 6 lcnt06 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2096h gpt loco count result register 7 lcnt07 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2098h gpt loco count result register 8 lcnt08 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 209ah gpt loco count result register 9 lcnt09 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 209ch gpt loco count result register 10 lcnt10 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 209eh gpt loco count result register 11 lcnt11 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 20a0h gpt loco count result register 12 lcnt12 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 20a2h gpt loco count result register 13 lcnt13 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 20a4h gpt loco count result register 14 lcnt14 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 20a6h gpt loco count result register 15 lcnt15 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 20a8h gpt loco count upper permissible deviation register lcntdu 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 20aah gpt loco count lower permissible deviation register lcntdl 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2100h gpt0 general pwm timer i/o control register gtior 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2102h gpt0 general pwm timer interrupt output setting register gtintad 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2104h gpt0 general pwm timer control register gtcr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2106h gpt0 general pwm timer buffer enable register gtber 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2108h gpt0 general pwm timer count direction registe r gtudc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 210ah gpt0 general pwm timer interrupt, a/d converter start request skipping setting register gtitc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 210ch gpt0 general pwm timer status register gtst 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 210eh gpt0 general pwm timer counter gtcnt 16 16 2 to 5 pclka 2, 3 iclk 000c 2110h gpt0 general pwm timer compare capture register a gtccra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2112h gpt0 general pwm timer compare capture register b gtccrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2114h gpt0 general pwm timer compare capture register c gtccrc 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2116h gpt0 general pwm timer compare capture register d gtccrd 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2118h gpt0 general pwm timer compare capture register e gtccre 16 16, 32 2 to 5 pclka 2, 3 iclk table 4.1 list of i/o registers (address order) (37/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 92 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 211ah gpt0 general pwm timer compare capture register f gtccrf 16 16, 32 2 to 5 pclka 2, 3 iclk gpt 000c 211ch gpt0 general pwm timer cycle setting register gtpr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 211eh gpt0 general pwm timer cycle setting buffer register gtpbr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2120h gpt0 general pwm timer cycle setting double- buffer register gtpdbr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2124h gpt0 a/d converter start request timing register a gtadtra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2126h gpt0 a/d converter start request timing buffer register a gtadtbra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2128h gpt0 a/d converter start request timing double- buffer register a gtadtdbra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 212ch gpt0 a/d converter start request timing register b gtadtrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 212eh gpt0 a/d converter start request timing buffer register b gtadtbrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2130h gpt0 a/d converter start request timing double- buffer register b gtadtdbrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2134h gpt0 general pwm timer output negate control register gtoncr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2136h gpt0 general pwm timer dead time control register gtdtcr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2138h gpt0 general pwm timer dead time value register u gtdvu 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 213ah gpt0 general pwm timer dead time value register d gtdvd 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 213ch gpt0 general pwm timer dead time buffer register u gtdbu 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 213eh gpt0 general pwm timer dead time buffer register d gtdbd 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2140h gpt0 general pwm timer output protection function status register gtsos 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2142h gpt0 general pwm timer output protection function temporary release register gtsotr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2180h gpt1 general pwm timer i/o control register gtior 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2182h gpt1 general pwm timer interrupt output setting register gtintad 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2184h gpt1 general pwm timer control register gtcr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2186h gpt1 general pwm timer buffer enable register gtber 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2188h gpt1 general pwm timer count direction register gtudc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 218ah gpt1 general pwm timer interrupt, a/d converter start request skipping setting register gtitc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 218ch gpt1 general pwm timer status register gtst 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 218eh gpt1 general pwm timer counter gtcnt 16 16 2 to 5 pclka 2, 3 iclk 000c 2190h gpt1 general pwm timer compare capture register a gtccra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2192h gpt1 general pwm timer compare capture register b gtccrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2194h gpt1 general pwm timer compare capture register c gtccrc 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2196h gpt1 general pwm timer compare capture register d gtccrd 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2198h gpt1 general pwm timer compare capture register e gtccre 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 219ah gpt1 general pwm timer compare capture register f gtccrf 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 219ch gpt1 general pwm timer cycle setting register gtpr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 219eh gpt1 general pwm timer cycle setting buffer register gtpbr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21a0h gpt1 general pwm timer cycle setting double- buffer register gtpdbr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21a4h gpt1 a/d converter start request timing register a gtadtra 16 16, 32 2 to 5 pclka 2, 3 iclk table 4.1 list of i/o registers (address order) (38/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 93 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 21a6h gpt1 a/d converter start request timing buffer register a gtadtbra 16 16, 32 2 to 5 pclka 2, 3 iclk gpt 000c 21a8h gpt1 a/d converter start request timing double- buffer register a gtadtdbra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21ach gpt1 a/d converter start request timing register b gtadtrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21aeh gpt1 a/d converter start request timing buffer register b gtadtbrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21b0h gpt1 a/d converter start request timing double- buffer register b gtadtdbrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21b4h gpt1 general pwm timer output negate control register gtoncr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21b6h gpt1 general pwm timer dead time control register gtdtcr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21b8h gpt1 general pwm timer dead time value register u gtdvu 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21bah gpt1 general pwm timer dead time value register d gtdvd 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21bch gpt1 general pwm timer dead time buffer register u gtdbu 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21beh gpt1 general pwm timer dead time buffer register d gtdbd 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21c0h gpt1 general pwm timer output protection function status register gtsos 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 21c2h gpt1 general pwm timer output protection function temporary release register gtsotr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2200h gpt2 general pwm timer i/o control register gtior 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2202h gpt2 general pwm timer interrupt output setting register gtintad 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2204h gpt2 general pwm timer control register gtcr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2206h gpt2 general pwm timer buffer enable register gtber 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2208h gpt2 general pwm timer count direction register gtudc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 220ah gpt2 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 220ch gpt2 general pwm timer status register gtst 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 220eh gpt2 general pwm timer counter gtcnt 16 16 2 to 5 pclka 2, 3 iclk 000c 2210h gpt2 general pwm timer compare capture register a gtccra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2212h gpt2 general pwm timer compare capture register b gtccrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2214h gpt2 general pwm timer compare capture register c gtccrc 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2216h gpt2 general pwm timer compare capture register d gtccrd 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2218h gpt2 general pwm timer compare capture register e gtccre 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 221ah gpt2 general pwm timer compare capture register f gtccrf 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 221ch gpt2 general pwm timer cycle setting register gtpr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 221eh gpt2 general pwm timer cycle setting buffer register gtpbr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2220h gpt2 general pwm timer cycle setting double- buffer register gtpdbr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2224h gpt2 a/d converter start request timing register a gtadtra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2226h gpt2 a/d converter start request timing buffer register a gtadtbra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2228h gpt2 a/d converter start request timing double- buffer register a gtadtdbra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 222ch gpt2 a/d converter start request timing register b gtadtrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 222eh gpt2 a/d converter start request timing buffer register b gtadtbrb 16 16, 32 2 to 5 pclka 2, 3 iclk table 4.1 list of i/o registers (address order) (39/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 94 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 2230h gpt2 a/d converter start request timing double- buffer register b gtadtdbrb 16 16, 32 2 to 5 pclka 2, 3 iclk gpt 000c 2234h gpt2 general pwm timer output negate control register gtoncr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2236h gpt2 general pwm timer dead time control register gtdtcr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2238h gpt2 general pwm timer dead time value register u gtdvu 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 223ah gpt2 general pwm timer dead time value register d gtdvd 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 223ch gpt2 general pwm timer dead time buffer register u gtdbu 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 223eh gpt2 general pwm timer dead time buffer register d gtdbd 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2240h gpt2 general pwm timer output protection function status register gtsos 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2242h gpt2 general pwm timer output protection function temporary release register gtsotr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2280h gpt3 general pwm timer i/o control register gtior 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2282h gpt3 general pwm timer interrupt output setting register gtintad 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2284h gpt3 general pwm timer control register gtcr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2286h gpt3 general pwm timer buffer enable register gtber 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 2288h gpt3 general pwm timer count direction register gtudc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 228ah gpt3 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 228ch gpt3 general pwm timer status register gtst 16 8, 16, 32 2 to 5 pclka 2, 3 iclk 000c 228eh gpt3 general pwm timer counter gtcnt 16 16 2 to 5 pclka 2, 3 iclk 000c 2290h gpt3 general pwm timer compare capture register a gtccra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2292h gpt3 general pwm timer compare capture register b gtccrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2294h gpt3 general pwm timer compare capture register c gtccrc 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2296h gpt3 general pwm timer compare capture register d gtccrd 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2298h gpt3 general pwm timer compare capture register e gtccre 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 229ah gpt3 general pwm timer compare capture register f gtccrf 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 229ch gpt3 general pwm timer cycle setting register gtpr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 229eh gpt3 general pwm timer cycle setting buffer register gtpbr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22a0h gpt3 general pwm timer cycle setting double- buffer register gtpdbr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22a4h gpt3 a/d converter start request timing register a gtadtra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22a6h gpt3 a/d converter start request timing buffer register a gtadtbra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22a8h gpt3 a/d converter start request timing double- buffer register a gtadtdbra 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22ach gpt3 a/d converter start request timing register b gtadtrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22aeh gpt3 a/d converter start request timing buffer register b gtadtbrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22b0h gpt3 a/d converter start request timing double- buffer register b gtadtdbrb 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22b4h gpt3 general pwm timer output negate control register gtoncr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22b6h gpt3 general pwm timer dead time control register gtdtcr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22b8h gpt3 general pwm timer dead time value register u gtdvu 16 16, 32 2 to 5 pclka 2, 3 iclk table 4.1 list of i/o registers (address order) (40/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 95 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 22bah gpt3 general pwm timer dead time value register d gtdvd 16 16, 32 2 to 5 pclka 2, 3 iclk gpt 000c 22bch gpt3 general pwm timer dead time buffer register u gtdbu 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22beh gpt3 general pwm timer dead time buffer register d gtdbd 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22c0h gpt3 general pwm timer output protection function status register gtsos 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 22c2h gpt3 general pwm timer output protection function temporary release register gtsotr 16 16, 32 2 to 5 pclka 2, 3 iclk 000c 2318h gpt0 gtioca rising output delay register gtdlyra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 231ah gpt0 gtiocb rising output delay register gtdlyrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 231ch gpt1 gtioca rising output delay register gtdlyra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 231eh gpt1 gtiocb rising output delay register gtdlyrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2320h gpt2 gtioca rising output delay register gtdlyra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2322h gpt2 gtiocb rising output delay register gtdlyrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2324h gpt3 gtioca rising output delay register gtdlyra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2326h gpt3 gtiocb rising output delay register gtdlyrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2328h gpt0 gtioca falling output delay register gtdlyfa 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 232ah gpt0 gtiocb falling output delay register gtdlyfb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 232ch gpt1 gtioca falling output delay register gtdlyfa 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 232eh gpt1 gtiocb falling output delay register gtdlyfb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2330h gpt2 gtioca falling output delay register gtdlyfa 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2332h gpt2 gtiocb falling output delay register gtdlyfb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2334h gpt3 gtioca falling output delay register gtdlyfa 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2336h gpt3 gtiocb falling output delay register gtdlyfb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2800h gptb general pwm timer software start register gtstr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2804h gptb general pwm timer hardware source start control register gthscr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2806h gptb general pwm timer hardware source clear control register gthccr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2808h gptb general pwm timer hardware start source select register gthssr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 280ah gptb general pwm timer hardware stop/clear source select register gthpsr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 280ch gptb general pwm timer write-protection register gtwp 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 280eh gptb general pwm timer sync register gtsync 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2810h gptb general pwm timer external trigger input interrupt register gtetint 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2814h gptb general pwm timer buffer operation disable register gtbdr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2818h gptb general pwm timer start write-protection register gtswp 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2880h gptb loco count control register lccr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2882h gptb loco count status register lcst 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. table 4.1 list of i/o registers (address order) (41/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 96 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 2884h gptb loco count value register lcnt 16 8, 16, 32 2 to 5 pclka 2, 3 iclk gpt not present in versions with 64, or 48 pins. 000c 2886h gptb loco count result average register lcnta 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 2888h gptb loco count result register 0 lcnt00 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 288ah gptb loco count result register 1 lcnt01 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64, or 48 pins. 000c 288ch gptb loco count result register 2 lcnt02 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 288eh gptb loco count result register 3 lcnt03 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2890h gptb loco count result register 4 lcnt04 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2892h gptb loco count result register 5 lcnt05 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2894h gptb loco count result register 6 lcnt06 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2896h gptb loco count result register 7 lcnt07 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2898h gptb loco count result register 8 lcnt08 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 289ah gptb loco count result register 9 lcnt09 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 289ch gptb loco count result register 10 lcnt10 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 289eh gptb loco count result register 11 lcnt11 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 28a0h gptb loco count result register 12 lcnt12 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 28a2h gptb loco count result register 13 lcnt13 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 28a4h gptb loco count result register 14 lcnt14 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 28a6h gptb loco count result register 15 lcnt15 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 28a8h gptb loco count upper permissible deviation register lcntdu 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 28aah gptb loco count lower permissible deviation register lcntdl 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2900h gpt4 general pwm timer i/o control register gtior 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2902h gpt4 general pwm timer interrupt output setting register gtintad 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2904h gpt4 general pwm timer control register gtcr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2906h gpt4 general pwm timer buffer enable register gtber 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2908h gpt4 general pwm timer count direction register gtudc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 290ah gpt4 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 290ch gpt4 general pwm timer status register gtst 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 290eh gpt4 general pwm timer counter gtcnt 16 16 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2910h gpt4 general pwm timer compare capture register a gtccra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2912h gpt4 general pwm timer compare capture register b gtccrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2914h gpt4 general pwm timer compare capture register c gtccrc 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2916h gpt4 general pwm timer compare capture register d gtccrd 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2918h gpt4 general pwm timer compare capture register e gtccre 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (42/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 97 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 291ah gpt4 general pwm timer compare capture register f gtccrf 16 16, 32 2 to 5 pclka 2, 3 iclk gpt not present in versions with 64 or 48 pins. 000c 291ch gpt4 general pwm timer cycle setting register gtpr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 291eh gpt4 general pwm timer cycle setting buffer register gtpbr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2920h gpt4 general pwm timer cycle setting double- buffer register gtpdbr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2924h gpt4 a/d converter start request timing register a gtadtra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2926h gpt4 a/d converter start request timing buffer register a gtadtbra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2928h gpt4 a/d converter start request timing double- buffer register a gtadtdbra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 292ch gpt4 a/d converter start request timing register b gtadtrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 292eh gpt4 a/d converter start request timing buffer register b gtadtbrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2930h gpt4 a/d converter start request timing double- buffer register b gtadtdbrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2934h gpt4 general pwm timer output negate control register gtoncr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2936h gpt4 general pwm timer dead time control register gtdtcr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2938h gpt4 general pwm timer dead time value register u gtdvu 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 293ah gpt4 general pwm timer dead time value register d gtdvd 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 293ch gpt4 general pwm timer dead time buffer register u gtdbu 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 293eh gpt4 general pwm timer dead time buffer register d gtdbd 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2940h gpt4 general pwm timer output protection function status register gtsos 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2942h gpt4 general pwm timer output protection function temporary release register gtsotr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2980h gpt5 general pwm timer i/o control register gtior 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2982h gpt5 general pwm timer interrupt output setting register gtintad 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2984h gpt5 general pwm timer control register gtcr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2986h gpt5 general pwm timer buffer enable register gtber 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2988h gpt5 general pwm timer count direction register gtudc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 298ah gpt5 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 298ch gpt5 general pwm timer status register gtst 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 298eh gpt5 general pwm timer counter gtcnt 16 16 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2990h gpt5 general pwm timer compare capture register a gtccra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2992h gpt5 general pwm timer compare capture register b gtccrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2994h gpt5 general pwm timer compare capture register c gtccrc 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2996h gpt5 general pwm timer compare capture register d gtccrd 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2998h gpt5 general pwm timer compare capture register e gtccre 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 299ah gpt5 general pwm timer compare capture register f gtccrf 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 299ch gpt5 general pwm timer cycle setting register gtpr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (43/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 98 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 299eh gpt5 general pwm timer cycle setting buffer register gtpbr 16 16, 32 2 to 5 pclka 2, 3 iclk gpt not present in versions with 64 or 48 pins. 000c 29a0h gpt5 general pwm timer cycle setting double- buffer register gtpdbr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29a4h gpt5 a/d converter start request timing register a gtadtra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29a6h gpt5 a/d converter start request timing buffer register a gtadtbra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29a8h gpt5 a/d converter start request timing double- buffer register a gtadtdbra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29ach gpt5 a/d converter start request timing register b gtadtrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29aeh gpt5 a/d converter start request timing buffer register b gtadtbrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29b0h gpt5 a/d converter start request timing double- buffer register b gtadtdbrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29b4h gpt5 general pwm timer output negate control register gtoncr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29b6h gpt5 general pwm timer dead time control register gtdtcr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29b8h gpt5 general pwm timer dead time value register u gtdvu 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29bah gpt5 general pwm timer dead time value register d gtdvd 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29bch gpt5 general pwm timer dead time buffer register u gtdbu 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29beh gpt5 general pwm timer dead time buffer register d gtdbd 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29c0h gpt5 general pwm timer output protection function status register gtsos 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 29c2h gpt5 general pwm timer output protection function temporary release register gtsotr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a00h gpt6 general pwm timer i/o control register gtior 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a02h gpt6 general pwm timer interrupt output setting register gtintad 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a04h gpt6 general pwm timer control register gtcr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a06h gpt6 general pwm timer buffer enable register gtber 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a08h gpt6 general pwm timer count direction register gtudc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a0ah gpt6 general pwm timer interrupt, a/d converter start request skipping setting register gtitc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a0ch gpt6 general pwm timer status register gtst 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a0eh gpt6 general pwm timer counter gtcnt 16 16 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a10h gpt6 general pwm timer compare capture register a gtccra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a12h gpt6 general pwm timer compare capture register b gtccrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a14h gpt6 general pwm timer compare capture register c gtccrc 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a16h gpt6 general pwm timer compare capture register d gtccrd 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a18h gpt6 general pwm timer compare capture register e gtccre 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a1ah gpt6 general pwm timer compare capture register f gtccrf 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a1ch gpt6 general pwm timer cycle setting register gtpr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a1eh gpt6 general pwm timer cycle setting buffer register gtpbr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a20h gpt6 general pwm timer cycle setting double- buffer register gtpdbr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (44/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 99 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 2a24h gpt6 a/d converter start request timing register a gtadtra 16 16, 32 2 to 5 pclka 2, 3 iclk gpt not present in versions with 64 or 48 pins. 000c 2a26h gpt6 a/d converter start request timing buffer register a gtadtbra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a28h gpt6 a/d converter start request timing double- buffer register a gtadtdbra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a2ch gpt6 a/d converter start request timing register b gtadtrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a2eh gpt6 a/d converter start request timing buffer register b gtadtbrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a30h gpt6 a/d converter start request timing double- buffer register b gtadtdbrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a34h gpt6 general pwm timer output negate control register gtoncr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a36h gpt6 general pwm timer dead time control register gtdtcr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a38h gpt6 general pwm timer dead time value register u gtdvu 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a3ah gpt6 general pwm timer dead time value register d gtdvd 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a3ch gpt6 general pwm timer dead time buffer register u gtdbu 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a3eh gpt6 general pwm timer dead time buffer register d gtdbd 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a40h gpt6 general pwm timer output protection function status register gtsos 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a42h gpt6 general pwm timer output protection function temporary release register gtsotr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a80h gpt7 general pwm timer i/o control register gtior 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a82h gpt7 general pwm timer interrupt output setting register gtintad 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a84h gpt7 general pwm timer control register gtcr 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a86h gpt7 general pwm timer buffer enable register gtber 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a88h gpt7 general pwm timer count direction register gtudc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a8ah gpt7 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a8ch gpt7 general pwm timer status register gtst 16 8, 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a8eh gpt7 general pwm timer counter gtcnt 16 16 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a90h gpt7 general pwm timer compare capture register a gtccra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a92h gpt7 general pwm timer compare capture register b gtccrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a94h gpt7 general pwm timer compare capture register c gtccrc 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a96h gpt7 general pwm timer compare capture register d gtccrd 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a98h gpt7 general pwm timer compare capture register e gtccre 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a9ah gpt7 general pwm timer compare capture register f gtccrf 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a9ch gpt7 general pwm timer cycle setting register gtpr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2a9eh gpt7 general pwm timer cycle setting buffer register gtpbr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2aa0h gpt7 general pwm timer cycle setting double- buffer register gtpdbr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2aa4h gpt7 a/d converter start request timing register a gtadtra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2aa6h gpt7 a/d converter start request timing buffer register a gtadtbra 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (45/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 100 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c 2aa8h gpt7 a/d converter start request timing double- buffer register a gtadtdbra 16 16, 32 2 to 5 pclka 2, 3 iclk gpt not present in versions with 64 or 48 pins. 000c 2aach gpt7 a/d converter start request timing register b gtadtrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2aaeh gpt7 a/d converter start request timing buffer register b gtadtbrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2ab0h gpt7 a/d converter start request timing double- buffer register b gtadtdbrb 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2ab4h gpt7 general pwm timer output negate control register gtoncr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2ab6h gpt7 general pwm timer dead time control register gtdtcr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2ab8h gpt7 general pwm timer dead time value register u gtdvu 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2abah gpt7 general pwm timer dead time value register d gtdvd 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2abch gpt7 general pwm timer dead time buffer register u gtdbu 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2abeh gpt7 general pwm timer dead time buffer register d gtdbd 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2ac0h gpt7 general pwm timer output protection function status register gtsos 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c 2ac2h gpt7 general pwm timer output protection function temporary release register gtsotr 16 16, 32 2 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3002h dpc software start setting register 0 softstart 0 16 16 3 to 5 pclka 2, 3 iclk dpc not present in versions with 64 or 48 pins. 000c3006h dpc software start setting register 1 softstart 1 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c300ah dpc software start setting register 2 softstart 2 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c300eh dpc software start setting register 3 softstart 3 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3012h dpc reference value setting register 0 votarget 0 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3016h dpc reference value setting register 1 votarget 1 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c301ah dpc reference value setting register 2 votarget 2 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c301eh dpc reference value setting register 3 votarget 3 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3022h dpc reference value select register refsel 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3026h dpc pwm channel setting register chlsel 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c302ah dpc control enable setting register enable 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c302eh dpc control calculation parameter setting register kp0 paramkp0 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3032h dpc control calculation parameter setting register ki0 paramki0 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3036h dpc control calculation parameter setting register kq0 paramkq0 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c303ah dpc control calculation parameter setting register kf0 paramkf0 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c303eh dpc control calculation parameter setting register kp1 paramkp1 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3042h dpc control calculation parameter setting register ki1 paramki1 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3046h dpc control calculation parameter setting register kq1 paramkq1 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c304ah dpc control calculation parameter setting register kf1 paramkf1 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c304eh dpc control calculation parameter setting register kp2 paramkp2 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3052h dpc control calculation parameter setting register ki2 paramki2 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. table 4.1 list of i/o registers (address order) (46/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 101 of 186 mar 31, 2016 rx63t group 4. i/o registers 000c3056h dpc control calculation parameter setting register kq2 paramkq2 16 16 3 to 5 pclka 2, 3 iclk dpc not present in versions with 64 or 48 pins. 000c305ah dpc control calculation parameter setting register kf2 paramkf2 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c305eh dpc control calculation parameter setting register kp3 paramkp3 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3062h dpc control calculation parameter setting register ki3 paramki3 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3066h dpc control calculation parameter setting register kq3 paramkq3 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c306ah dpc control calculation parameter setting register kf3 paramkf3 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c306ch dpc control calculation result higher-order bits store register 0 resultu0 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c306eh dpc control calculation result lower-order bits store register 0 resultl0 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3070h dpc control calculation result higher-order bits store register 1 resultu1 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3072h dpc control calculation result lower-order bits store register 1 resultl1 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3074h dpc control calculation result higher-order bits store register 2 resultu2 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3076h dpc control calculation result lower-order bits store register 2 resultl2 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3078h dpc control calculation result higher-order bits store register 3 resultu3 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c307ah dpc control calculation result lower-order bits store register 3 resultl3 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c307eh dpc input code monitor enable register tmonen 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3082h dpc maximum input code monitor register 0 tmonmax0 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3086h dpc minimum input code monitor register 0 tmonmin0 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c308ah dpc maximum input code monitor register 1 tmonmax1 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c308eh dpc minimum input code monitor register 1 tmonmin1 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3092h dpc maximum input code monitor register 2 tmonmax2 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c3096h dpc minimum input code monitor register 2 tmonmin2 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c309ah dpc maximum input code monitor register 3 tmonmax3 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c309eh dpc minimum input code monitor register 3 tmonmin3 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c30a2h dpc overvoltage output error judgment thresh- old setting register 0 errvth0 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c30a6h dpc overvoltage output error judgment thresh- old setting register 1 errvth1 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c30aah dpc overvoltage output error judgment thresh- old setting register 2 errvth2 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c30aeh dpc overvoltage output error judgment thresh- old setting register 3 errvth3 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 000c30b2h dpc pwm shut-down at overvoltage output error setting register errdwn 16 16 3 to 5 pclka 2, 3 iclk not present in versions with 64 or 48 pins. 007f c402h flash flash mode register fmodr 8 8 2, 3 fclk 2, 3 iclk rom/ e2 dataflash memory 007f c410h flash flash access status register fastat 8 8 2, 3 fclk 2, 3 iclk 007f c411h flash flash access error interrupt enable register faeint 8 8 2, 3 fclk 2, 3 iclk 007f c412h flash flash ready interrupt enable register frdyie 8 8 2, 3 fclk 2, 3 iclk rom 0 07f c440h flash e2 dataflash read enable register 0 dflre0 16 16 2, 3 fclk 2, 3 iclk e2 dataflash memory 007f c442h flash e2 dataflash read enable register 1 dflre1 16 16 2, 3 fclk 2, 3 iclk 007f c450h flash e2 dataflash p/e enable register 0 dflwe0 16 16 2, 3 fclk 2, 3 iclk 007f c452h flash e2 dataflash p/e enable register 1 dflwe1 16 16 2, 3 fclk 2, 3 iclk table 4.1 list of i/o registers (address order) (47/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 102 of 186 mar 31, 2016 rx63t group 4. i/o registers note: ? this table shows the maximum specifications of i/o register s. the i/o registers of individual products correspond to the list of functions given as table 1.2. for details, refer to table 1.2, comparison of functions for different packages. note 1. when the register is accessed while the usb is operating, a delay may be generated in accessing. note 2. odd addresses are not accessible in 16-bit units. obtain 16-bit access to the two registers by access to the address of tmocntl. note 3. pins usb0 and riic1 are not present in 112-pin products. note 4. pins usb0, riic1, and sci3 are not present in 100-pin products. note 5. pins gpt4 to gpt7, usb0, rspi1, riic1, sci2, sci3, ca n1, ad, and s12ad1 are not present in 64- and 48-pin products. 007f ffb0h flash flash status register 0 fstatr0 8 8 2, 3 fclk 2, 3 iclk rom 007f ffb1h flash flash status register 1 fstatr1 8 8 2, 3 fclk 2, 3 iclk 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2, 3 fclk 2, 3 iclk rom/ e2 dataflash memory 007f ffb4h flash flash protection register fprotr 16 16 2, 3 fclk 2, 3 iclk rom 007f ffb6h flash flash reset register fresetr 16 16 2, 3 fclk 2, 3 iclk 007f ffbah flash fcu command register fcmdr 16 16 2, 3 fclk 2, 3 iclk 007f ffc8h flash fcu processing switching register fcpsr 16 16 2, 3 fclk 2, 3 iclk 007f ffcah flash e2 dataflash blank check control register dflbccnt 16 16 2, 3 fclk 2, 3 iclk e2 dataflash memory 007f ffcch flash flash p/e status register fpestat 16 16 2, 3 fclk 2, 3 iclk rom 007f ffceh flash e2 dataflash blank check status register dflbcstat 16 16 2, 3 fclk 2, 3 iclk e2 dataflash memory 007f ffe8h flash peripheral clock notification regi ster pckar 16 16 2, 3 fclk 2, 3 iclk rom table 4.1 list of i/o registers (address order) (48/48) address module symbol register name register symbol number of bits access size number of access states module name remarks iclk ?? pclk iclk ? pclk
r01ds0087ej0220 rev.2.20 page 103 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.1 absolute maximum ratings caution: permanent damage to the lsi may result if absolute maximum ratings are exceeded. note 1. when the usb is not in use, do not leave the vcc_usb and vss_usb pins open. connect the vcc_usb pin to vcc, and the vss_usb pin to vss, respectively. note 2. when the a/d converter is not in use, do not leav e the avcc0, vrefh0, vrefl0, avss0, avcc, vref, and avss pins open. ? when the 12-bit a/d converter is not in use connect the avcc0 pin to avcc, the vrefh0 pin to vr ef, and the avss0 and vrefl0 pins to avss, respectively. ? when the 10-bit a/d converter is not in use connect the avcc pin to avcc0, the vref pin to vrefh0, and the avss pin to avss0, respectively. ? when the 12-bit a/d converter and 10-bit a/d converter are not in use connect the avcc0, vrefh0, avcc, and vref pins to vc c, and the avss0, vrefl0, and avss pins to vss, respectively. table 5.1 absolute maximum ratings conditions: vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v item symbol value unit power supply voltage vcc, pllvcc ?0.3 to +6.5 v usb power supply voltage vcc_usb* 1 ?0.3 to +6.5 v analog power supply voltage avcc0, avcc* 2 ?0.3 to +6.5 v reference power supply voltage vrefh0* 2 ?0.3 to avcc0 + 0.3 v vref* 2 ?0.3 to avcc0 + 0.3 v input voltage (except for ports 4 to 6, c, usb0_dp, and usb0_dm) v in ?0.3 to vcc + 0.3 v input voltage (usb0_dp and usb0_dm) v in ?0.3 to vcc_usb + 0.3 v input voltage (port 4) v in ?0.3 to avcc0 + 0.3 v input voltage (ports 5, 6, and c) v in ?0.3 to avcc + 0.3 v analog input voltage (port 4) v an ?0.3 to avcc0 + 0.3 v analog input voltage (ports 5, 6, and c) v an ?0.3 to avcc + 0.3 v operating temperature d version product t opr ?40 to +85 oc g version product t opr ?40 to +105 oc storage temperature t stg ?55 to +125 oc
r01ds0087ej0220 rev.2.20 page 104 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.2 dc characteristics note 1. this includes the multiplexed pin func tions, except for p25, p26, pb1, or pb2 when the riic input functions are in use, p22 to p24, p30, pa3 to pa5, pb0, pd0 to pd2, or pd6 when the rspi input functions are in use, and pd4 or pf3 when the tck input function is in use. table 5.2 dc characteristics (1) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 the following relation applies when the usb is in use under condition 1 or condition 2: vcc = pllvcc = vcc_usb = 3.0 to 3.6 v. t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions schmitt trigger input voltage can input pin irq input pin mtu3 input pin poe3 input pin sci input pin a/d trigger input pin gpt input pin res#, nmi v ih vcc 0.8 ? vcc + 0.3 v v il ?0.3 ? vcc 0.2 ? v t vcc 0.06 ? ? riic input pin (iicbus operating) v ih vcc 0.7 ? vcc + 0.3 v il ?0.3 ? vcc 0.3 ? v t vcc 0.05 ? ? usb0_vbus input pin v ih vcc 0.7 ? vcc + 0.3 v il ?0.3 ? vcc 0.2 ? v t vcc 0.06 ? ? port 4* 1 (also used as an analog port) v ih avcc0 0.8 ? avcc0 + 0.3 v il ?0.3 ? avcc0 0.2 ports 5, 6, and c* 1 (also used as an analog port) v ih avcc 0.8 ? avcc + 0.3 v il ?0.3 ? avcc 0.2 ports 0 to 3* 1 ports 7 to b* 1 ports d to g* 1 v ih vcc 0.8 ? vcc + 0.3 v il ?0.3 ? vcc 0.2 input high voltage (except for schmitt trigger input pin) md pin, emle v ih vcc 0.9 ? vcc + 0.3 v extal, wait#, tck rspi input pin vcc 0.8 ? vcc + 0.3 d0 to d15 vcc 0.7 ? vcc + 0.3 riic input pin (smbus operating) 2.1 ? vcc + 0.3 conditions 1 and 2 input low voltage (except for schmitt trigger input pin) md pin, emle v il ?0.3 ? vcc 0.1 v extal, wait#, tck rspi input pin ?0.3 ? vcc 0.2 d0 to d15 ?0.3 ? vcc 0.3 riic input pin (smbus operating) ?0.3 ? 0.8 conditions 1 and 2
r01ds0087ej0220 rev.2.20 page 105 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] table 5.3 dc characteristics (2) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 the following relation applies when the usb is in use under condition 1 or condition 2: vcc = pllvcc = vcc_usb = 3.0 to 3.6 v . t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions output high voltage all output pins (except for p52, p53, p60 to p65, p71 to p76, p90 to p95, and usb0_dpupe) v oh vcc ? 0.5 ? ? v i oh = ?1 ma p52, p53, and p60 to p65 avcc ? 0.5 ? ? i oh = ?1 ma usb0_dpupe vcc_usb ? 0.5 i oh = ?1 ma p71 to p76, and p90 to p95 vcc ? 1.0 ? ? i oh = ?5 ma output low voltage all output pins (except for p71 to p76, p90 to p95, and riic pins) v ol ??0.5vi ol = 1.0 ma p71 to p76, and p90 to p95 ? ? 1.1 i ol = 15 ma riic pins ? ? 0.4 i ol = 3 ma ??0.6 i ol = 6 ma input leakage current res#, md pin, emle, port 4, ports p50, p51, p54 to p57, and port c ? i in ? ??1.0 av in = 0 v, v in = vcc three-state leakage current (off state) port 0, port 1, ports p20 to p24, port 3, ports p52, p53, ports 6 to a, ports pb0, pb3 to pb7, and ports d to g ? i tsi ? ??1.0 av in = 0 v, v in = vcc ports p25, p26, pb1, and pb2 ??5.0 input capacitance all output pins (except for p25, p26, pb1, and pb2) c in ? ? 15 pf v in = 0 v, f = 1 mhz, t a = 25 oc ports p25, p26, pb1, and pb2 ??30
r01ds0087ej0220 rev.2.20 page 106 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] note 1. supply current values are with all output pins unloaded. note 2. measured with clocks suppl ied to the peripheral functions. this does not include the bgo operation. note 3. i cc depends on f (iclk) as follows. (iclk: pclk = 8:4) i cc max = 0.6 f + 10 (max) i cc typ = 0.3 f + 10 (normal) i cc max = 0.45 f + 10 (sleep mode) note 4. measured with clocks not supplied to the peripheral functions. this does not include the bgo operation. note 5. incremented if data is written to or erased from the on- chip rom or on-chip data-flash memory for data storage during th e program execution. note 6. the values are for reference. table 5.4 dc characteristics (3) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 the following relation applies when the usb is in use under condition 1 or condition 2: vcc = pllvcc = vcc_usb = 3.0 to 3.6 v. t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions supply current * 1 during operation max. * 2 i cc * 3 ? ? 70 ma iclk = 100 mhz pclka = 100 mhz pclkb = 50 mhz pclkc = 100 mhz pclkd = 50 mhz fclk = 50 mhz normal * 4 ?40? increased by bgo operation * 5 ?15? sleep mode 40 55 all-module-clock-stop mode * 6 20 30 during standby software standby mode ? 0.10 3 ma deep software standby mode ?2060 a analog power supply current during 12-bit a/d conversion (per unit) ai cc0 ?1.54.2ma programmable gain amplifier (per channel) ? 1 1.5 ma window comparator (per channel) ? 0.5 0.7 ma waiting for 12-bit a/d conversion (all units) ? 0.1 8 a during 10-bit a/d conversion (per channel) ai cc ?0.91.4ma during d/a conversion (per unit) 0.1 4 a waiting for 10-bit a/d, d/a conversion (all units) ?0.1 4 a reference power supply current during 12-bit a/d conversion (per unit) ai refh0 ?1.62.5ma waiting for 12-bit a/d conversion (all units) ? 0.1 1.5 a during 10-bit a/d conversion (per channel) ai ref ?0.20.3ma during d/a conversion (per unit) 1 1.5 ma waiting for 10-bit a/d, d/a conversion (all units) ?0.11.2 a vcc rising gradient sv cc ??20ms/ v
r01ds0087ej0220 rev.2.20 page 107 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] note 1. usb0_dp and usb0_dm are not included. note 2. for pins p71 to p76 and p90 to p95, i ol = 15 ma (max.) and ?i oh = 5 ma (max.). however, if several of the pins are to supply i ol and ?i oh of more than 2.0 ma at the same time, the number of pins should be six or less. caution: to protect the mcu?s reliability, the output current values should not exceed the values in this table. table 5.5 permissible output currents note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: v cc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 the following relation applies when the usb is in use under condition 1 or condition 2: vcc = pllvcc = vcc_usb = 3.0 to 3.6 v. t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit permissible output low current (average value per pin) all output pins (except for p71 to p76, p90 to p95, and riic pins)* 1 i ol ??2.0ma riic pins i ol ??6.0ma p71 to p76, and p90 to p95* 2 i ol ? ? 15.0 ma permissible output low current (max. value per pin) all output pins (except for p71 to p76, p90 to p95, and riic pins)* 1 i ol ??4.0ma riic pins i ol ??6.0ma p71 to p76, and p90 to p95* 2 i ol ? ? 15.0 ma permissible output low current (total) total of output pins i ol ??110ma permissible output high current (average value per pin) all output pins (except for p71 to p76, p90 to p95, and usb0_dpupe pin)* 1 ?i oh ??2.0ma usb0_dpupe pin ?i oh ??3.0ma p71 to p76, and p90 to p95* 2 ?i oh ??5.0ma permissible output high current (max. value per pin) all output pins (except for p71 to p76, p90 to p95)* 1 ?i oh ??4.0ma p71 to p76, and p90 to p95* 2 ?i oh ??5.0ma permissible output high current (total) ?i oh ??35ma
r01ds0087ej0220 rev.2.20 page 108 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] note: ? please contact renesas electronics sales office for derat ing of operation under ta = +85c to +105c. derating is the systematic reduction of load for th e sake of improved reliability. note 1. the total power consumption of the whole chip including output current. table 5.6 permissible power consumption (g version product only) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0v avcc0 = avcc = 4.0 to 5.5v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +105c. ta is common to conditions 1 to 3. item symbol typ. max. unit test conditions total permissible power consumption* 1 pd ? 345 mw 85c < ta 105c
r01ds0087ej0220 rev.2.20 page 109 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.3 ac characteristics note 1. the pclk must run at a frequency of at least 24 mhz when the usb is in use. table 5.7 operation frequency value note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss =pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit operation frequency system clock (iclk) f ? ? 100 mhz peripheral module clock (pclk) * 1 ??5 0 timer module clock (pclka) ? ? 100 ad clock (pclkc) ? ? 100 s12ad clock (pclkd) ? ? 50 flashif clock (fclk) ? ? 50 external bus clock (bclk) ? ? 50 bclk pin output ? ? 25 usb clock (uclk) ? ? 48
r01ds0087ej0220 rev.2.20 page 110 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.3.1 reset timing figure 5.1 reset input timing at power-on figure 5.2 reset input timing table 5.8 reset timing note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions res# pulse width power-on t reswp 2 ? ? ms figure 5.1 deep software standby mode t reswd 1 ? ? ms figure 5.2 software standby mode t resws 1??ms programming or erasure of the rom or e2 dataflash memory or blank checking of the e2 dataflash memory t reswf 200 ? ? s other than above t resw 200 ? ? s wait time after res# cancellation t reswt 59 ? 60 t cyc internal reset time (independent watchdog timer reset, watchdog timer reset, software reset) t resw2 112 ? 120 t cyc vcc res# t reswp internal reset t reswt res# internal reset t reswt t reswd, t resws, t resw
r01ds0087ej0220 rev.2.20 page 111 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.3.2 clock timing note 1. this is the time until the clock is used after clearing the main clock oscillator stop bit (mosccr.mostp) to 0 (selectin g operation). note 2. when using a main clock, ask the manuf acturer of the oscillator to evaluate its oscillation. refer to the results of eva luation provided by the manufacturer for th e oscillation stabi lization time. note 3. this is calculated from the formula below, where n is the number of cycles set by the moscwtcr.msts[4:0] bits. table 5.9 clock timing note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions bclk pin output cycle time only condition 3 t bcyc 20 ? ? ns figure 5.3 other than condition 3 t bcyc 40 ? ? ns bclk pin output high pulse width t ch 5??ns bclk pin output low pulse width t cl 5??ns bclk pin output rising time t cr ?? 5ns bclk pin output falling time t cf ?? 5ns extal external clock input cycle time t excyc 70 ? ? ns figure 5.4 extal external clock input high pulse width t exh 35 ? ? ns extal external clock input low pulse width t exl 35 ? ? ns extal external clock rising time t exr ?? 5ns extal external clock falling time t exf ?? 5ns extal external clock input wait time* 1 t exwt 1??ms main clock oscillator oscillation frequency f main 8 ? 12.5 mhz main clock oscillation stabilization time (crystal) t mainosc ?? * 2 ms figure 5.5 main clock oscillation stabili zation wait time (crystal) t mainoscwt ?? * 3 ms loco, iwdtclk clock cycle time t lococyc 6.96 8 9.4 s loco, iwdtclk clock oscillation frequency f loco 106.25 125 143.75 khz loco, iwdtclk clock oscillatio n stabilization wait time t locowt ?? 20 s figure 5.6 pll clock frequency f pll 104 ? 200 mhz pll clock oscillation stabiliza tion time pll operation started after main clock oscillation has settled t pll1 ? ? 500 s figure 5.7 pll clock oscillation stabilization wait time t pllwt1 ?? * 4 ms pll clock oscillation stabiliza tion time pll operation started before main clock oscillation has settled t pll2 ??t mainosc + t pll1 ms figure 5.8 pll clock oscillation stabilization wait time t pllwt2 ?? * 4 ms t mainoscwt n +16384 f main t mainosc = +
r01ds0087ej0220 rev.2.20 page 112 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] note 4. this is calculated from the formula below, where n is the number of cycles set by the pllwtcr.psts[4:0] bits. figure 5.3 bclk pin output timing figure 5.4 extal external clock input timing figure 5.5 main clock oscillation start timing figure 5.6 loco, iwdtclk clock oscillation start timing t pllwt1 n +131072 f pll t pll1 = + n +131072 f pll = t pllwt2 t pll2 + n +131072 f pll t mainosc t pll1 + = + t cf t ch t bcyc , t sdcyc t cr t cl bclk pin output test conditions: voh = vcc 0.7, vol = vcc 0.3, ioh = ?1.0 ma, iol = 1.0 ma, c = 30 pf t exh t excyc extal external clock input vcc 0.5 t exl t exr t exf main clock oscillation output mosccr.mostp t mainosc main clock t mainoscwt loco, iwdtclk clock lococr.lcstp, ilococr.ilcstp t locowt
r01ds0087ej0220 rev.2.20 page 113 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.7 pll clock oscillation start timing (pll is operated after main clock oscillation has settled) figure 5.8 pll clock oscillation st art timing (pll is operated befo re main clock oscillation has settled) pllcr2.pllen pll clock mosccr.mostp t mainosc main clock oscillation output pll circuit output t pll1 t pllwt1 mosccr.mostp pll circuit output pllcr2.pllen t pll2 t mainosc main clock oscillation output pll clock t pllwt2
r01ds0087ej0220 rev.2.20 page 114 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.3.3 timing of recovery from low power consumption modes note: ? the wait time varies depending on the state in which each oscillator was when the wait instruction was executed. the reco very time when multiple oscillators are operating is the same period as that when the oscillator, which takes the longest time for recovery among the operating oscillators, is operating alone. figure 5.9 software standby mode cancellation timing table 5.10 timing of recovery from low power consumption modes note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions recovery time after cancellation of software standby mode crystal resonator connected to main clock oscillator main clock oscillator operating t sbymc 10 ? ? ms figure 5.9 main clock oscillator and pll circuit operating t sbypc 10 ? ? ms external clock input to main clock oscillator main clock oscillator operating t sbyex 1??ms main clock oscillator and pll circuit operating t sbype 1??ms low-speed clock oscillator or iwdt-specific low- speed clock oscillator operating t sbylo ? ? 800 s recovery time after cancellation of deep software standby mode t dsby ? ? 1 ms figure 5.10 wait time after cancellation of deep software standby mode t dsbywt 45 ? 46 t cyc oscillator iclk irq software standby mode t sbymc, t sbypc, t sbyex, t sbype, t sbysc, t sbyho, t sbylo
r01ds0087ej0220 rev.2.20 page 115 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.10 deep software standby mode cancellation timing oscillator irq internal reset reset exception handling start deep software standby mode deep software standby reset t dsby t dsbywt
r01ds0087ej0220 rev.2.20 page 116 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.3.4 control signal timing figure 5.11 nmi interrupt input timing figure 5.12 irq interrupt input timing table 5.11 control signal timing note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions nmi pulse width t nmiw 200 ? ? ns t c (pclk) 2 200 ns, figure 5.11 t c (pclk) 2 ? ? ns t c (pclk) > 200 ns, figure 5.11 irq pulse width t irqw 200 ? ? ns t c (pclk) 200 ns, figure 5.12 t c (pclk) 2 ? ? ns t c (pclk) > 200 ns, figure 5.12 nmi t nmiw irq t irqw
r01ds0087ej0220 rev.2.20 page 117 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.3.5 bus timing table 5.12 bus timing (1) condition: vcc = pllvcc = vcc_usb = avcc0 = avcc = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc t a = t opr output load conditions: v oh = vcc x 0.5, v ol = vcc x 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. max. unit test conditions address delay time t ad ? 30 ns figure 5.13 to figure 5.16 byte control delay time t bcd ?3 0n s cs# delay time t csd ?3 0n s rd# delay time t rsd ?3 0n s read data setup time t rds 20 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?3 0n s write data delay time t wdd ?3 5n s write data hold time t wdh 0?n s wait# setup time t wts 20 ? ns figure 5.17 wait# hold time t wth 0?n s table 5.13 bus timing (2) condition: vcc = pllvcc = avcc0 = avcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc t a = t opr output load conditions: v oh = vcc x 0.5, v ol = vcc x 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. max. unit test conditions address delay time t ad ? 15 ns figure 5.13 to figure 5.16 byte control delay time t bcd ?1 5n s cs# delay time t csd ?1 5n s rd# delay time t rsd ?1 5n s read data setup time t rds 15 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?1 5n s write data delay time t wdd ?1 5n s write data hold time t wdh 0?n s wait# setup time t wts 15 ? ns figure 5.17 wait# hold time t wth 0?n s
r01ds0087ej0220 rev.2.20 page 118 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.13 external bus timing/normal read cycle (bus clock synchronized) a19 to a1 cs3# to cs0# t ad bclk a19 to a0 d15 to d0 (read) byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd rd# (read) t rsd t rsd t ad t rdh t rds t ad t ad t bcd t w1 t w2 t end t n1 t h rdon:1 csrwait:2 csroff:1 cson:0
r01ds0087ej0220 rev.2.20 page 119 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.14 external bus timing/normal write cycle (bus clock synchronized) a19 to a1 cs3# to cs0# t ad bclk a19 to a0 byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd t ad t ad t ad t bcd d15 to d0 (write) wr1#, wr0#, wr# (write) t wrd t wrd t wdh t wdd t w1 t w2 t end t n1 t h wron:1 wdon:1* 1 cswwait:2 cswoff:1 wdoff:1* 1 cson:0 note1. be sure to specify wdon and wdoff as at leas t one cycl e of bclk.
r01ds0087ej0220 rev.2.20 page 120 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.15 external bus timing/page read cycle (bus clock synchronized) figure 5.16 external bus timing/page write cycle (bus clock synchronized) a19 to a1 cs3# to cs0# t ad bclk a19 to a0 d15 to d0 (read) byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd rd# (read) t rsd t rsd t rdh t rds t ad t bcd t w1 t w2 t end t pw1 t pw2 t ad t ad t rsd t rsd t rdh t rds t rsd t rsd t rdh t rds t pw3 t end t n1 t n2 t ad t ad t ad t ad rdon:1 csrwait:3 csroff:2 t pw1 t pw2 t end csprwait:3 rdon:1 csprwait:3 rdon:1 cson:0 t pw3 t w3 a19 to a1 cs3# to cs0# t ad bclk a19 to a0 byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd t ad t bcd t w1 d15 to d0 (write) wr1#, wr0#, wr# (write) t wrd t wrd t wdh t wdd t w2 t end t pw1 t pw2 t ad t ad t wrd t wrd t wdh t wdd t wrd t wrd t wdh t wdd t dw1 t end t pw1 t pw2 t end t n1 t h t dw1 t ad t ad t ad t ad wron:1 wdon:1* 1 cswwait:2 cspwwait:2 wdoff:1* 1 cspwwait:2 wdoff:1* 1 wdoff:1* 1 cson:0 note 1. be sure to specify wdon and wdoff as at least one cycle of bclk. wron:1 wdon:1* 1 wron:1 wdon:1* 1 cswoff:1
r01ds0087ej0220 rev.2.20 page 121 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.17 external bus timing/external wait control table 5.14 bus timing (multiplexed bus) (3) condition: pllvcc = vcc_usb = avcc0 = avcc = vref = 3.0 to 3.6 v vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v, vrefh0 = 3.0 v to avcc0 t a = t opr output load conditions: v oh = vcc x 0.5, v ol = vcc x 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. max. unit test conditions address delay time t ad ? 35 ns figure 5.18, figure 5.19 byte control delay time t bcd ?3 0n s cs# delay time t csd ?3 0n s rd# delay time t rsd ?3 0n s ale delay time t aled ?3 0n s read data setup time t rds 20 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?3 0n s write data delay time t wdd ?3 5n s write data hold time t wdh 0?n s wait# setup time t wts 20 ? ns figure 5.17 wait# hold time t wth 0.0 ? ns t wts t wth t wts t wth csrwait:3 cswwait:3 bclk a19 to a0 cs3# to cs0# rd# (read) wr# (write) wait# t w1 t w2 (t end )t end t w3 t n1 t h external wait
r01ds0087ej0220 rev.2.20 page 122 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.18 example of external bus timi ng/read access operation (multiplexed) table 5.15 bus timing (multiplexed bus) (4) condition: vcc = pllvcc = avcc0 = avcc = vref = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v, vrefh0 = 4.0 v to avcc0 t a = t opr output load conditions: v oh = vcc x 0.5, v ol = vcc x 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. max. unit test conditions address delay time t ad ? 15 ns figure 5.18, figure 5.19 byte control delay time t bcd ?1 5n s cs# delay time t csd ?1 5n s rd# delay time t rsd ?1 5n s ale delay time t aled ?1 5n s read data setup time t rds 15 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?1 5n s write data delay time t wdd ?1 5n s write data hold time t wdh 0?n s wait# setup time t wts 15 ? ns figure 5.17 wait# hold time t wth 0.0 ? ns address/data bus (a15/d15 to a0/d0) data read (rd#) t ad bclk address bus address latch (ale) chip select (cs3# to cs0#) t aled t w1 t w2 t n1 t ad t ad t rds t n2 t rsd t rsd t w3 t w4 t w5 t end t a1 t a1 t an address cycle data cycle t rdh t aled t csd t csd
r01ds0087ej0220 rev.2.20 page 123 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.19 example of external bus timi ng/write access oper ation (multiplexed) address/data bus (a15/d15 to a0/d0) data write (wrm#) t ad bclk address bus address latch (ale) chip select (cs3# to cs0#) t aled t w1 t w2 t n1 t ad t ad t n2 t wrd t wrd t w3 t w4 t w5 t end t a1 t a1 t an address cycle data cycle t aled t csd t csd t wdd t wdh t n3
r01ds0087ej0220 rev.2.20 page 124 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.3.6 timing of on-chi p peripheral modules table 5.16 timing of on-chi p peripheral modules (1) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min. max. unit* 1 test conditions i/o ports input data pulse width t prw 1.5 ? t pcyc figure 5.22 mtu3 input capture input pulse width single-edge setting t ticw 3?t pacyc figure 5.23 both-edge setting 5 ? input capture input fall time t tictf ?0.1 s/v when input capture at rising edge, or input capture at both edges is selected. timer clock pulse width single-edge setting t tckwh, t tckwl 3?t pacyc figure 5.25 both-edge setting 5 ? phase counting mode 5? timer clock input fall time t tcktf ?0.1 s/v poe3 poe# input pulse width t poew 1.5 ? t pcyc figure 5.28 gpt input capture input pulse width single-edge setting t gticw 3?t pacyc figure 5.26 both-edge setting 5 ? input capture input fall time t gtictf ?0.1 s/v when input capture at rising edge, or input capture at both edges is selected. when count operation is started at rising edge, or count operation is started at both edges is selected. when count operation is stopped at rising edge, or count operation is stopped at both edges is selected. when counter is cleared at rising edge, or counter is cleared at both edges is selected. external trigger input pulse width single-edge setting t otetw 3?t pacyc figure 5.27 both-edge setting 5 ? external trigger input fall time t gtetrgtf ?0.1 s/v when count operation is started at rising edge, or count operation is started at both edges is selected. when count operation is stopped at rising edge, or count operation is stopped at both edges is selected. when counter is cleared at rising edge, or counter is cleared at both edges is selected.
r01ds0087ej0220 rev.2.20 page 125 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] note 1. t pcyc : pclk cycle, t pacye : pclka cycle note 2. t cac : cac count clock source cycle. table 5.16 timing of on-chi p peripheral modules (2) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min. max. unit* 1 test conditions sci input clock cycle asynchronous t scyc 4?t pcyc c = 30 pf figure 5.29 clock synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?20ns input clock fall time t sckf ?20ns output clock cycle asynchronous t scyc 16 ? t pcyc clock synchronous 4 ? output clock pulse width t sckw 0.4 0.6 t scyc output clock rise time t sckr ?20ns output clock fall time t sckf ?20ns transmit data delay time clock synchronous t txd ? 40 ns figure 5.30 receive data setup time clock synchronous t rxs 40 ? ns receive data hold time clock synchronous t rxh 40 ? ns receive data fall time t tictf ?0.1 s/v when noise cancellation function is not used. a/d converter 10-bit a/d converter trigger input pulse width t trgw 1.5 ? t pcyc figure 5.31 12-bit a/d converter trigger input pulse width 1.5 ? cac cacref input pulse width t pcyc t cac * 2 t cacref 4.5 t cac + 3 t pcyc ?ns t pcyc > t cac * 2 5 t cac + 6.5 t pcyc ?ns cacref input fall time t cacreftf ?0.1 s/v
r01ds0087ej0220 rev.2.20 page 126 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] note 1. t pcyc : pclk cycle table 5.16 timing of on-chi p peripheral modules (3) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss =pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. high drive output is selected by the drive capacity control register. item symbol min. max. unit* 1 test conditions rspi rspck clock cycle master t spcyc 2 4096 t pcyc c = 30 pf, figure 5.32 slave 8 4096 rspck clock high pulse width master t spckwh (t spcyc ? t spckr ? t spckf ) / 2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf ) / 2 ? rspck clock low pulse width master t spckwl (t spcyc ? t spckr ? t spckf ) / 2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf ) / 2 ? rspck clock rise/fall time output t spckr, t spckf ?5 n s input ? 1 s rspck clock fall time input t spckf ?0 . 1 s/v data input setup time master t su 4 ? ns c = 30 pf, figure 5.33 to figure 5.40 slave 20 ? t pcyc ? data input hold time master pclkb division ratio set to a value other than 1/2 t h t pcyc ?n s pclkb division ratio set to 1/2 t hf 0? slave t h 20 + 2 t pcyc ? ssl setup time master t lead 18t spcyc slave 4 ? t pcyc ssl hold time master t lag 18t spcyc slave 4 ? t pcyc data output delay time master t od ?1 0n s slave ? 3 t pcyc + 40 data output hold time master t oh 0?n s slave 0 ? successive transmission delay time master t td t spcyc + 2 t pcyc 8 t spcyc + 2 t pcyc ns slave 4 t pcyc ? mosi and miso rise/fall time output t dr, t df ?5 n s input ? 1 s ssl rise/fall time output t sslr, t sslf ?1 5n s input ? 1 s slave access time t sa ?4 t pcyc figure 5.39 and figure 5.40 slave output release time t rel ?3 t pcyc
r01ds0087ej0220 rev.2.20 page 127 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] note 1. t pcyc : pclk cycle table 5.16 timing of on-chi p peripheral modules (4) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min. max. unit* 1 test conditions simple spi sck clock cycle output (master) t spcyc 4 65536 t pcyc c = 30 pf, figure 5.30 sck clock cycle input (slave) 8 65536 sck clock high pulse width t spckwh 0.4 0.6 t spcyc sck clock low pulse width t spckwl 0.4 0.6 t spcyc sck clock rise/fall time t spckr, t spckf ?2 0n s data input setup time t su 40 ? ns c = 30 pf, figure 5.31 to figure 5.38 data input hold time t h 40 ? ns ss input setup time t lead 6?t pcyc ss input hold time t lag 6?t pcyc data output delay time t od ?4 0n s data output hold time t oh ?10 ? ns data rise/fall time t dr, t df ?2 0n s ss input rise/fall time t sslr, t sslf ?2 0n s slave access time t sa ?5 t pcyc c = 30 pf, figure 5.37 and figure 5.38 slave output release time t rel ?5 t pcyc
r01ds0087ej0220 rev.2.20 page 128 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] note: ? t iiccyc : riic internal reference clock (iic ? ) cycle note 1. the value within parentheses is applicable when the value of the icmr3.nf[1:0] bits is 11b wh ile the digital filter is e nabled by the setting icfer.nfe = 1. note 2. cb is the total capacitance of the bus lines. table 5.16 timing of on-chi p peripheral modules (5) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min.* 1, * 2 max. unit test conditions riic (standard-mode) scl input cycle time t scl 6(12) t iiccyc + 1300 ? ns figure 5.36 scl input high pulse width t sclh 3(6) t iiccyc + 300 ? ns scl input low pulse width t scll 3(6) t iiccyc + 300 ? ns scl, sda input rise time t sr ? 1000 ns scl, sda input fall time t sf ? 300 ns scl, sda input spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda input bus free time t buf 3(6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns restart condition input setup time t stas 1000 ? ns stop condition input setup time t stos 1000 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf riic (fast-mode) scl input cycle time t scl 6(12) t iiccyc + 600 ? ns scl input high pulse width t sclh 3(6) t iiccyc + 300 ? ns scl input low pulse width t scll 3(6) t iiccyc + 300 ? ns scl, sda input rise time t sr 20 + 0.1c b 300 ns scl, sda input fall time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda input bus free time t buf 3(6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns restart condition input setup time t stas 300 ? ns stop condition input setup time t stos 300 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf
r01ds0087ej0220 rev.2.20 page 129 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] note 1. the value in parentheses is used when icmr3.nf[1:0] are set to 11b while a digital filter is enabled with icfer.nfe = 1. note 2. cb indicates the total capacity of the bus line. note 3. t pcyc : pclk cycle 5.3.7 timing of pwm delay generation circuit note 1. this value is correct when the difference between each code and the next is a resolution of one bit (1 lsb). table 5.16 timing of on-chi p peripheral modules (6) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min.* 1, * 2 max. unit test conditions simple iic (standard-mode) scl, sda input rise time t sr ? 1000 ns figure 5.36 scl, sda input fall time t sf ? 300 ns scl, sda input spike pulse removal time t sp 04 t pcyc ns data input setup time t sdas 250 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf simple iic (fast-mode) scl, sda input rise time t sr 20 + 0.1c b 300 ns scl, sda input fall time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 04 t pcyc ns data input setup time t sdas 100 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf table 5.17 timing of the pw m delay generation circuit condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = topr. ta is common to conditions 1 to 3. item symbol typ. max. unit test conditions resolution ? 312.5 ? ps pclka = 100 mhz dnl* 1 ? ? 2.0 ? lsb
r01ds0087ej0220 rev.2.20 page 130 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.20 i/o port input timing figure 5.21 mtu3 input/output timing figure 5.22 mtu3 clock input timing figure 5.23 gpt input capture input timing figure 5.24 gpt external trigger input timing port pclk t prw input capture input pclka t ticw mtclka to mtclkd pclka t tckwl t tckwh input capture input pclka t gticw external trigger input pclka t gtew
r01ds0087ej0220 rev.2.20 page 131 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.25 poe3# input timing figure 5.26 sck clock input timing figure 5.27 sci input/output timing: clock synchronous mode figure 5.28 ad converter external trigger input timing poen# input pclk t poew t sckw t sckr t sckf t scyc sckn (n = 0 to 3, 12) t txd t rxs t rxh txdn rxdn sckn n = 0 to 3, 12 adtrg# adtrg0# adtrg1# pclk t trgw
r01ds0087ej0220 rev.2.20 page 132 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.29 rspi clock timing and simple spi clock timing figure 5.30 rspi timing (master, cpha = 0) (bit rate: pclkb division rati o set to a value other than 1/2) and simple spi timing (master, ckph = 1) sckn master select output sckn slave select input t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 x v cc , v ol = 0.3 x v cc , v ih = 0.7 x v cc , v il = 0.3 x v cc (n = 0 to 3, 12) simple spi rspckm master select output rspckm slave select input (m = a, b) rspi ssln0 to 3 output rspckn cpol = 0 output rspckn cpol = 1 output mison input mosin output t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out rspi (n = a, b) sckm ckpol = 0 output sckm ckpol = 1 output smisom input simple spi (m = 0 to 3, 12) smosim output
r01ds0087ej0220 rev.2.20 page 133 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.31 rspi timing (master, cpha = 1) (bit rate: pclkb divi sion ratio set to 1/2) figure 5.32 rspi timing (master, cpha = 1) (bit rate: pclkb division rati o set to a value other than 1/2) and simple spi timing (master, ckph = 0) ssln0 to 3 output rspckn cpol = 0 output rspckn cpol = 1 output mison input mosin output t dr, t df t su t hf t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out t hf (n = a, b) ssln0 to 3 output rspckn cpol = 0 output rspckn cpol = 1 output mison input mosin output t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od (n = a, b) sckm ckpol = 0 output sckm ckpol = 1 output smisom input smosim output (m = 0 to 3, 12) rspi simple spi
r01ds0087ej0220 rev.2.20 page 134 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.33 rspi timing (master, cpha = 1) (bit rate: pclkb divi sion ratio set to 1/2) figure 5.34 rspi timing (slave, cpha = 0) and simple spi timing (slave, ckph = 1) ssln0 to 3 output rspckn cpol = 0 output rspckn cpol = 1 output mison input mosin output t dr, t df t su t hf t lead t td t lag t sslr, t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od (n = a, b) rspi t h ssln0 input rspckn cpol = 0 input rspckn cpol = 1 input mosin input mison output t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel (n = a, b) ssm# input sckm ckpol = 0 input sckm ckpol = 1 input smosim input smisom output (m = 0 to 3, 12) rspi simple spi
r01ds0087ej0220 rev.2.20 page 135 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.35 rspi timing (slave, cpha = 1) and simple spi timing (slave, ckph = 0) figure 5.36 riic bus interface input/output timing and simple iic bus interface input/output timing ssln0 input rspckn cpol = 0 input rspckn cpol = 1 input mison output mosin input t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out (n = a, b) ssm# input sckm cpol = 0 input sckm cpol = 1 input smisom output smosim input (m = 0 to 3, 12) rspi simple spi sdan scln v ih v il t stah t sclh t scll p * 1 s * 1 t sf t sr t scl t sdah t sdas t stas t sp t stos p * 1 t buf note 1. s, p, and sr indicate the following conditions. s: start condition p: stop condition sr: restart condition test conditions v ih = v cc 0.7, v il = v cc 0.3 v ol = 0.6v, i ol = 6ma sr * 1 riic simple iic (n = 0, 1) ssdam ssclm (m = 0 to 3,12)
r01ds0087ej0220 rev.2.20 page 136 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.4 usb characteristics figure 5.37 dp and dm ou tput timing (full-speed) figure 5.38 test circuit (full-speed) table 5.18 on-chip usb full-speed characteristics (dp and dm pin characteristics) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min. max. unit test conditions input characteristics input high level voltage v ih 2.0 ? v figure 5.37 figure 5.38 input low level voltage v il ?0.8v differential input sensitivity v di 0.2 ? v | dp ? dm | differential common mode range v cm 0.8 2.5 v output characteristics output high level voltage v oh 2.8 3.6 v i oh = ?200 a output low level voltage v ol 0.0 0.3 v i ol = 2 ma cross-over voltage v crs 1.3 2.0 v rise time t lr 420ns fall time t lf 420ns rise/fall time ratio t lr / t lf 90 111.11 % t lr / t lf output resistance z drv 28 44 ? rs = 24 ? included dp, dm t lf t lr 90% 10% 10% 90% v crs observation point 24 ? 24 ? 50 pf 50 pf dp dm
r01ds0087ej0220 rev.2.20 page 137 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.5 a/d conversion characteristics note 1. the conversion time includes the sampling time and the co mparison time. as the test condi tions, the number of sampling s tates is indicated. table 5.19 10-bit a/d conversion characteristics (1) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vs s = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vs s = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item min. typ. max. unit test conditions resolution 10 10 10 bit conversion time* 1 (operation at adclk = 100 mhz) with 0.1-f external capaci- tor an0 to an7 0.5 ? ? s sampling in 25 states other channels 0.75 ? ? s sampling in 50 states without 0.1-f external capaci- tor permissible sig- nal source impedance (max.) = 1 k ? an0 to an7 0.6 ? ? s sampling in 35 states other channels 0.75 ? ? s sampling in 50 states analog input capacitance ? ? 6 pf integral nonlinearity error ? ? 3.0 lsb offset error ? ? 2.0 lsb full-scale error ? ? 3.0 lsb quantization error ? 0.5 ? lsb absolute accuracy ? ? 6.0 lsb
r01ds0087ej0220 rev.2.20 page 138 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] note 1. the conversion time includes the sampling time and the co mparison time. as the test condi tions, the number of sampling s tates is indicated. table 5.20 10-bit a/d conversion characteristics (2) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vs s = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vs s = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr is common to conditions 1 to 3. item min. typ. max. unit test conditions resolution 10 10 10 bit conversion time* 1 (operation at adclk = 50 mhz) without 0.1-f external capaci- tor permissible sig- nal source impedance (max.) = 1 k ? an0 to an7 0.8 ? ? s sampling in 15 states other channels 1.0 ? ? s sampling in 25 states analog input capacitance ? ? 6 pf integral nonlinearity error ? ? 2.0 lsb offset error ? ? 2.0 lsb full-scale error ? ? 3.0 lsb quantization error ? 0.5 ? lsb absolute accuracy ? ? 4.0 lsb
r01ds0087ej0220 rev.2.20 page 139 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] note 1. the conversion time includes the sampling time and the co mparison time. as the test condi tions, the number of sampling s tates is indicated. note 1. the conversion time includes the sampling time and the co mparison time. as the test condi tions, the number of sampling s tates is indicated. table 5.21 12-bit a/d conversion characteristics (1) condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vs s = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 t a = t opr item min. typ. max. unit test conditions resolution 12 12 12 bit conversion time* 1 (adclk = 25 mhz) without 0.1-f external capacitor permissible signal source impedance (max.) = 1.0 k ? 2.0 ? ? s sampling in 20 states analog input capacitance ? ? 8 pf sample and hold circuit in use integral nonlinearity error ? ? 4.0 lsb avin = 0.25 to av refh ?0.25 offset error ? ? 4.0 lsb full-scale error ? ? 4.0 lsb quantization error ? 0.5 ? lsb absolute accuracy ? ? 8.0 lsb sample and hold circuit not in use integral nonlinearity error ? ? 3.0 lsb avin = av refl to av refh offset error ? ? 3.0 lsb full-scale error ? ? 3.0 lsb quantization error ? 0.5 ? lsb absolute accuracy ? ? 6.0 lsb table 5.22 12-bit a/d conversion characteristics (2) note: common standard values for conditions not given in the table are listed as ?condition 1? and ?condition 2? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 2: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 2 and 3. item min. typ. max. unit test conditions resolution 12 12 12 bit conversion time* 1 (adclk = 50 mhz) without 0.1-f external capacitor permissible signal source impedance (max.) = 1.0 k ? 1.0 ? ? s sampling in 20 states analog input capacitance ? ? 6 pf sample and hold circuit in use integral nonlinearity error ? ? 6.0 lsb avin = 0.25 to av refh ?0.25 offset error ? ? 6.0 lsb full-scale error ? ? 6.0 lsb quantization error ? 0.5 ? lsb absolute accuracy ? ? 8.0 lsb sample and hold circuit not in use integral nonlinearity error ? ? 3.0 lsb avin = av refl to av refh offset error ? ? 3.0 lsb full-scale error ? ? 3.0 lsb quantization error ? 0.5 ? lsb absolute accuracy ? ? 6.0 lsb
r01ds0087ej0220 rev.2.20 page 140 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] table 5.23 characteristics of th e programmable gain amplifier note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions analog input capacitance c in ?? 8p f input offset voltage v off ?? 8m v input voltage range (v in ) gain 2.000 v in 0.050 avcc ? 0.450 avcc v gain 2.500 0.047 avcc 0.360 avcc gain 3.077 0.045 avcc 0.292 avcc gain 3.636 0.042 avcc 0.247 avcc gain 4.000 0.040 avcc 0.212 avcc gain 4.444 0.036 avcc 0.191 avcc gain 5.000 0.033 avcc 0.170 avcc gain 5.714 0.031 avcc 0.148 avcc gain 6.667 0.029 avcc 0.127 avcc gain 10.000 0.025 avcc 0.08 avcc gain 13.333 0.023 avcc ? 0.06 avcc slew rate sr 10 ? ? v/ s gain error gain 2.000 ? ? ? 1 % gain 2.500 ? ? 1 gain 3.077 ? ? 1 gain 3.636 ? ? 1.5 gain 4.000 ? ? 1.5 gain 4.444 ? ? 2 gain 5.000 ? ? 2 gain 5.714 ? ? 2 gain 6.667 ? ? 3 gain 10.000 ? ? 4 gain 13.333 ? ? 4
r01ds0087ej0220 rev.2.20 page 141 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] table 5.24 comparator characteristics note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions analog input capacitance c in ??8 p f refh pin offset voltage v off ??5 m v refl pin offset voltage ? ? 5 mv refh input voltage range v in 1.7 ? avcc ? 0.3 v refl input voltage range 0.3 ? avcc ? 1.7 v refh reply time t cr ? ? 500 ns vi = vref25mv refl reply time t cf ? ? 500 ns
r01ds0087ej0220 rev.2.20 page 142 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.6 d/a conversion characteristics table 5.25 d/a conversion characteristics note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item min. typ. max. unit test conditions resolution 10 10 10 bit conversion time ? ? 3.0 s 20-pf capacitive load absolute accuracy ? 2.0 4.0 lsb 2-m ? resistive load ?? 3 . 0l s b4 - m ? resistive load ?? 2 . 0l s b1 0 - m ? resistive load ro output resistance ? 3.6 ? k ?
r01ds0087ej0220 rev.2.20 page 143 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.7 power-on reset circuit and voltage detecti on circuit characteristics note 1. # in symbol v det1_# indicates the value of the lvdlvlr.lvd1lvl[3:0] bits. note 2. # in symbol v det2_# indicates the value of the lvdlvlr.lvd2lvl[3:0] bits. note 3. the minimum vcc down time indicates the time when vc c is below the minimum value of voltage detection levels v por , v det1 , and v det2 for the por/ lvd. table 5.26 power-on reset circuit and voltage detection circuit characteristics (1) note: common standard values for conditions not given in the table are listed as ?condition 1? and ?condition 2? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 and 2. item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) v por 2.46 2.58 2.7 v figure 5.41 voltage detection circuit (lvd0) v det0 2.7 2.82 2.94 figure 5.42 voltage detection circuit (lvd1)* 1 v det1_8 2.75 2.90 3.05 figure 5.43 v det1_9 2.70 2.85 3.00 v det1_a 2.73 2.88 3.03 voltage detection circuit (lvd2)* 2 v det2_8 2.75 2.9 3.05 figure 5.44 v det2_9 2.70 2.85 3.00 v det2_a 2.73 2.88 3.03 internal reset time power-on reset (por) t por 9.7 ms figure 5.41 voltage detection circuit (lvd0) t lvd0 9.7 figure 5.42 voltage detection circuit (lvd1) t lvd1 0.9 figure 5.43 voltage detection circuit (lvd2) t lvd2 0.9 figure 5.44 minimum vcc down time* 3 t voff 200 ? ? s figure 5.41 and figure 5.42 response delay time t det 200 s lvd operation stabilization time (after lvd is enabled) td (e-a) 3 s figure 5.41 to figure 5.44 hysteresis width (lvd1 and lvd2) v lvh 80 mv
r01ds0087ej0220 rev.2.20 page 144 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] note 1. # in symbol v det1_# indicates the value of the lvdlvlr.lvd1lvl[3:0] bits. note 2. # in symbol v det2_# indicates the value of the lvdlvlr.lvd2lvl[3:0] bits. note 3. the minimum vcc down time indicates the time when vc c is below the minimum value of voltage detection levels v por , v det1 , and v det2 for the por/ lvd. figure 5.39 power-on reset timing figure 5.40 voltage detection circuit timing (v det0 ) table 5.27 power-on reset circuit and voltage detection circuit characteristics (2) condition: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) v por 3.6 3.8 4.0 v figure 5.41 voltage detection circuit (lvd0) v det0 4.0 4.2 4.4 figure 5.42 voltage detection circuit (lvd1)* 1 v det1_8 4.59 4.77 4.95 figure 5.43 v det1_9 4.05 4.23 4.41 v det1_a 4.32 4.50 4.68 voltage detection circuit (lvd2)* 2 v det2_8 4.59 4.77 4.95 figure 5.44 v det2_9 4.05 4.23 4.41 v det2_a 4.32 4.50 4.68 internal reset time power-on reset (por) t por 9.7 ms figure 5.41 voltage detection circuit (lvd0) t lvd0 9.7 figure 5.42 voltage detection circuit (lvd1) t lvd1 0.9 figure 5.43 voltage detection circuit (lvd2) t lvd2 0.9 figure 5.44 minimum vcc down time* 3 t voff 200 ? ? s figure 5.41 to figure 5.44 response delay time t det 200 s lvd operation stabilization time (after lvd is enabled) td (e-a) 3 s figure 5.41 to figure 5.44 hysteresis width (lvd1 and lvd2) v lvh 80 mv internal reset signal (active-low) vcc t voff t det t por t det t por t det v por t voff t lvd0 t det v det0 vcc internal reset signal (active-low)
r01ds0087ej0220 rev.2.20 page 145 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.41 voltage detection circuit timing (v det1 ) figure 5.42 voltage detection circuit timing (v det2 ) t voff v det1_# (# = 8, 9, a) vcc t det t det t lvd1 t d(e-a) lvd1e lvd1 comparator output lvd1cmpe lvd1mon internal reset signal (active-low) when lvd1rn = l when lvd1rn = h v lvh t lvd1 t voff v det2_# (# = 8, 9, a) vcc t det t det t lvd2 t d(e-a) lvd2e lvd2 comparator output lvd2cmpe lvd2mon internal reset signal (active-low) when lvd2rn = l when lvd2rn = h v lvh t lvd2
r01ds0087ej0220 rev.2.20 page 146 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.8 oscillation stop detecti on circuit characteristics figure 5.43 oscillation stop detection timing table 5.28 oscillation stop detection circuit characteristics note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions detection time t dr ? ? 1.0 ms figure 5.43 t dr main clock or pll clock ostdsr.ostdf loco clock iclk
r01ds0087ej0220 rev.2.20 page 147 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.9 rom (flash memory for code storage) characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 1000), erasing can be performed n times for each block. for instance, when 128-byte programming is performed 16 times for different addresses in 2-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (ove rwriting is prohibited). note 2. the value is obtained from the reliability test. table 5.29 rom (flash memory for code storage) characteristics (1) condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 temperature range for the programming/erasure operation: t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions reprogram/erase cycle* 1 n pec 1000 ? ? times data hold time t drp 30* 2 ? ? year ta = +85c table 5.30 rom (flash memory for code storage) characteristics (2) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 temperature range for the programming/erasure operation: t a = t opr . t a is common to conditions 1 to 3. item symbol fclk = 4 mhz 20 mhz fclk 50 mhz unit min. typ. max. min. typ. max. programming time n pec ? 100 times 128 bytes t p128 ? 2.8 28 ? 1 10 ms 4 kbytes t p4k ? 63 140 ? 23 50 ms 16 kbytes t p16k ? 252 560 ? 90 200 ms programming time n pec > 100 times 128 bytes t p128 ? 3.4 33.6 ? 1.2 12 ms 4 kbytes t p4k ? 75.6 168 ? 27.6 60 ms 16 kbytes t p16k ? 302.4 672 ? 108 240 ms erasure time n pec ? 100 times 4 kbytes t e4k ? 50 120 ? 25 60 ms 16 kbytes t e16k ? 200 480 ? 100 240 ms erasure time n pec > 100 times 4 kbytes t e4k ? 60 144 ? 30 72 ms 16 kbytes t e16k ? 240 576 ? 120 288 ms suspend delay time during programming t spd ? ? 400 ? ? 120 s first suspend delay time during erasing (in suspend priority mode) t sesd1 ? ? 300 ? ? 120 s second suspend delay time during erasing (in suspend priority mode) t sesd2 ??1.7??1.7ms suspend delay time during erasing (in erasure priority mode) t seed ??1.7??1.7ms fcu reset time t fcur 35 ? ? 35 ? ? s
r01ds0087ej0220 rev.2.20 page 148 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 5.10 e 2 flash characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each bl ock. when the reprogram/erase cycle is n times (n = 100000), erasing can be performed n times for each block. for instance, when 128-byte programming is performed 16 times for different addresses in 2-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (ove rwriting is prohibited). note 2. the value is obtained from the reliability test. table 5.31 e 2 flash characteristics (1) condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 temperature range for the programming/erasure operation: t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions reprogram/erase cycle* 1 n dpec 100000 ? ? times data hold time t ddrp 30* 2 ? ? year ta = +85c table 5.32 e 2 flash characteristics (2) note: common standard values for conditions not given in th e table are listed as ?condition 1? to ?condition 3? below. condition 1: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 condition 2: vcc = pllvcc = vcc_usb = 2.7 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 condition 3: vcc = pllvcc = 4.0 to 5.5 v, vcc_usb = 3.0 to 3.6 v, vss = pllvss = vss_usb = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = vref = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0 temperature range for the programming/erasure operation: t a = t opr . t a is common to conditions 1 to 3. item symbol fclk = 4 mhz 20 mhz fclk 50 mhz unit min. typ. max. min. typ. max. programming time n dpec ? 100 times 2 bytes t dp2 ? 0.7 6 ? 0.25 2 ms programming time n dpec > 100 times 2 bytes t dp2 ? 0.7 6 ? 0.25 2 ms erasure time n dpec ? 100 times 32 bytes t de32 ?440?220ms erasure time n dpec > 100 times 32 bytes t de32 ?740?420ms blank check time 2 bytes t dbc2 ? ? 100 ? ? 30 s suspend delay time during programming t dspd ? ? 250 ? ? 120 s first suspend delay time during erasing (in suspend priority mode) t dsesd1 ? ? 250 ? ? 120 s second suspend delay ti me during erasing (in suspend priority mode) t dsesd2 ? ? 500 ? ? 300 s suspend delay time during erasing (in erasure priority mode) t dseed ? ? 500 ? ? 300 s
r01ds0087ej0220 rev.2.20 page 149 of 186 mar 31, 2016 rx63t group 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] figure 5.44 flash memory pr ogram/erase suspend timing fcu command fstatr0.frdy programming pulse ? suspension during programming fcu command fstatr0.frdy erasure pulse ? suspension during erasure in suspend priority mode fcu command fstatr0.frdy erasure pulse ? suspension during erasure in erasure priority mode program suspend ready not ready ready programming t spd erase suspend ready not ready ready t seed erasing erase suspend resume suspend ready not ready ready not ready t sesd1 t sesd2 erasing erasing
r01ds0087ej0220 rev.2.20 page 150 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] 6. electrical characteristics [64- and 48-pin versions] 6.1 absolute maximum ratings caution: permanent damage to the lsi may result if absolute maximum ratings are exceeded. note 1. ports 0, 1, 2, 3, 7, 9, a, b, and d are 5 v tolerant. note 2. when the a/d converter is not in use, do not leave the avcc0, vrefh0, vrefl0, and avss0 pins open. connect the avcc0 and vrefh0 pins to vcc, and the avss0 and vrefl0 pins to vss, respectively. table 6.1 absolute maximum ratings item symbol value unit power supply voltage vcc ?0.3 to +4.6 v input voltage (except for ports for 5 v tolerant* 1 and port 4) vin ?0.3 to vcc+0.3 v input voltage (port 4) vin ?0.3 to avcc0+0.3 v input voltage (ports for 5 v tolerant)* 1 vin ?0.3 to +5.8 v analog power supply voltage avcc0* 2 ?0.3 to +4.6 v reference power supply voltage vrefh0* 2 ?0.3 to avcc0+0.3 v analog input voltage (port 4) v an ?0.3 to avcc0+0.3 v operating temperature d version product topr ?40 to +85 c g version product topr ?40 to +105 c storage temperature tstg ?55 to +125 c
r01ds0087ej0220 rev.2.20 page 151 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] 6.2 dc characteristics note 1. ports 0, 1, 2, 3, 7, 9, a, b, and d are 5 v tolerant. table 6.2 dc characteristics (1) conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min. typ. max. unit test conditions schmitt trigger input voltage irq input pin mtu3 input pin poe3 input pin sci input pin a/d trigger input pin gpt input pin res#, nmi v ih vcc 0.8 ? vcc + 0.3 v v il ?0.3 ? vcc 0.2 ?v t vcc 0.06 ? ? riic input pin (iicbus operating) v ih vcc 0.7 ? 5.8 v il ?0.3 ? vcc 0.3 ?v t vcc 0.05 ? ? port 4 (also used as an analog port) v ih avcc0 0.8 ? avcc0 + 0.3 v il ?0.3 ? avcc00.2 ports for 5 v tolerant* 1 v ih vcc 0.8 ? 5.8 v il ?0.3 ? vcc 0.2 input high voltage (except for schmitt trigger input pin) md pin, emle v ih vcc 0.9 ? vcc + 0.3 extal, tck, rspi input pin vcc 0.8 ? vcc + 0.3 riic input pin (smbus operating) 2.1 ? vcc + 0.3 input low voltage (except for schmitt trigger input pin) md pin, emle v il ?0.3 ? vcc 0.1 extal, tck, rspi input pin ?0.3 ? vcc 0.2 riic input pin (smbus operating) ?0.3 ? 0.8 output high voltage all output pins v oh vcc ? 0.5 ? ? v i oh = ?1 ma output low voltage all output pins (except for riic pins) v ol ??0 . 5vi ol = 1.0 ma riic pins ? ? 0.4 i ol = 3 ma ??0.6 i ol = 6 ma input leakage current res#, md pin, emle, ports 4 and pe2 ? i in ? ??1 . 0 av in = 0v, v in = vcc three-state leakage current (off state) ports for 5v tolerant ? i tsi ? ??1 . 0 av in = 0v, v in = 5.5 v ??5.0 input capacitance all input pins (except for ports pb1 and pb2) c in ? ? 15 pf v in = 0v, f = 1 mhz, t a = 25oc ports pb1 and pb2 ? ? 30
r01ds0087ej0220 rev.2.20 page 152 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] note 1. supply current values are with all output pins unloaded. note 2. measured with clocks suppl ied to the peripheral functions. this does not include the bgo operation. note 3. i cc depends on f (iclk) as follows. (iclk: pclk = 8:4) icc max = 0.45 f + 15 (max) icc typ = 0.18 f + 7 (normal) icc max = 0.22 f + 13 (sleep mode) note 4. measured with clocks not supplied to the peripheral functions. this does not include the bgo operation. note 5. incremented if data is written to or erased from the on- chip rom or on-chip data-flash memory for data storage during th e program execution. note 6. the values are for reference. caution: to protect the mcu?s reliability, the output current values should not exceed the values in this table. note 1. riic pin: iol = 6 ma (max.) table 6.3 dc characteristics (2) conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min. typ. max. unit test conditions supply current* 1 during operation max. * 2 i cc * 3 ? ? 60 ma iclk = 100mhz pclka = 100mhz pclkb = 50mhz pclkd = 50mhz fclk = 50mhz normal * 4 ?25? increased by bgo operation* 5 ?15? sleep mode 25 35 all-module-clock-stop mode* 6 14 25 during standby software standby mode ? 0.2 6 ma deep software standby mode ?1640 a analog power supply current during 12-bit a/d conversion (sample & hold circuit in use) ai cc0 ?3 4 ma during 12-bit a/d conversion (sample & hold circuit not in use) ?2 3 ma window comparator (1-channel operation) 0.4 1 ma window comparator (3-channel operation) ? 0.5 1 ma waiting for 12-bit ad conversion ? 25 32 a reference power supply current during 12-bit a/d conversion ai refh0 ?0.60.7ma waiting for 12-bit a/d conversion ? 0.6 0.7 ma vcc rising gradient srvcc ? ? 20000 ms/v table 6.4 permissible output currents conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min. typ. max. unit permissible output low current (average value per pin) i ol ??2 . 0 *1 ma permissible output low current (max. value per pin) i ol ??4 . 0 *1 ma permissible output low current (total) i ol ??3 2m a permissible output high current (average value per pin) ?i oh ??2 . 0m a permissible output high current (max. value per pin) ?i oh ??4 . 0m a permissible output high current (total) ?i oh ??3 2m a
r01ds0087ej0220 rev.2.20 page 153 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] note: ? please contact renesas electronics sales office for derat ing of operation under ta = +85c to +105c. derating is the systematic reduction of load for th e sake of improved reliability. note 1. the total power consumption of the whole chip including output current. table 6.5 permissible power consumption (g version product only) condition: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 t a = t opr item symbol typ. max. unit test conditions total permissible power consumption* 1 pd ? 150 mw 85c < ta 105c 64-pin version pd ? 120 mw 85c < ta 105 c 48-pin version
r01ds0087ej0220 rev.2.20 page 154 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] 6.3 ac characteristics note 1. the fclk must run at a frequency of at least 4 mhz when changing the rom or e2 dataflash memory contents. 6.3.1 clock timing note 1. this is the time until the clock is used after clearing the main clock oscillator stop bit (mosccr.mostp) to 0 (selectin g operation). note 2. when using a main clock, ask the manuf acturer of the oscillator to evaluate its oscillation. refer to the results of eva luation provided by the manufacturer for t he oscillation stabi lization time. note 3. this is calculated from the formula below, where n is the number of cycles set by the moscwtcr.msts[4:0] bits. table 6.6 operation frequency value conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min. typ max. unit operation frequency system clock (iclk) f ? ? 100 mhz peripheral module clock pclk ? ? 50 timer module clock (pclka) ? ? 100 s12ad clock (pclkd) ? ? 50 flash clock (fclk) ?* 1 ?5 0 table 6.7 clock timing conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min typ max. unit test conditions extal external clock input cycle time t excyc 50 ? ? ns figure 6.1 extal external clock input high pulse width t exh 20 ? ? ns extal external clock input low pulse width t exl 20 ? ? ns extal external clock rising time t exr ?? 5ns extal external clock falling time t exf ?? 5ns extal external clock input wait time* 1 t exwt 1??ms main clock oscillator oscillation frequency f main 4?16mhz main clock oscillation stabilization time (crystal) t mainosc ???* 2 ms figure 6.2 main clock oscillation stabili zation wait time (crystal) t mainoscwt ???* 3 ms loco, iwdtclk clock cycle time t cyc 6.96 8 9.4 s loco, iwdtclk clock oscillation frequency f loco 106.25 125 143.75 khz loco, iwdtclk clock oscillatio n stabilization wait time t locowt ??20 s figure 6.2 pll clock oscillation stabiliza tion time pll operation started after main clock oscillation has settled t pll1 ? ? 500 s figure 6.4 pll clock oscillation stabilization wait time t pllwt1 ???* 4 ms pll clock oscillation stabilization time pll pll operation started before main clock oscillation has settled t pll2 ?? t mainosc + t pll1 ms figure 6.5 pll clock oscillation stabilization wait time t pllwt2 ???* 4 ms t mainoscwt n +16384 f main t mainosc = +
r01ds0087ej0220 rev.2.20 page 155 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] note 4. this is calculated from the formula below, where n is the number of cycles set by the pllwtcr.psts[4:0] bits. figure 6.1 extal external clock input timing figure 6.2 main clock oscillation start timing figure 6.3 loco, iwdtclk clock oscillation start timing figure 6.4 pll clock oscillation start timing (pll is operated after main clock oscillation has settled) t pllwt1 n +131072 f pll t pll1 = + n +131072 f pll = t pllwt2 t pll2 + n +131072 f pll t mainosc t pll1 + = + t exh t excyc extal external clock input vcc 0.5 t exl t exr t exf main clock oscillation output mosccr.mostp t mainosc main clock t mainoscwt t locowt loco, iwdtclk clock lococr.lcstp, ilococr.ilcstp pllcr2.pllen pll clock mosccr.mostp t mainosc main clock oscillation output pll circuit output t pll1 t pllwt1
r01ds0087ej0220 rev.2.20 page 156 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] figure 6.5 pll clock oscillation st art timing (pll is operated befo re main clock oscillation has settled) mosccr.mostp pll circuit output pllcr2.pllen t pll2 t mainosc main clock oscillation output pll clock t pllwt2
r01ds0087ej0220 rev.2.20 page 157 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] 6.3.2 reset timing figure 6.6 reset input timing at power-on figure 6.7 reset input timing table 6.8 reset timing conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min typ max. unit test conditions res# pulse width power-on t reswp 2 ? ? ms figure 6.6 deep software standby mode t reswd 1 ? ? ms figure 6.7 software standby mode t resws 1??ms other than above (except for programming or erasure of the rom or e2 dataflash memory or blank checking of the e2 dataflash memory) t resw 200 ? ? s wait time after res# cancellation t reswt 59 ? 60 t cyc internal reset time (independent watchdog timer reset, watchdog timer reset, software reset) t resw2 112 ? 120 t cyc vcc res# t reswp internal reset t reswt res# internal reset t reswt t reswd, t resws, t resw
r01ds0087ej0220 rev.2.20 page 158 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] 6.3.3 timing of recovery from low power consumption modes note: ? the wait time varies depending on the state in which each oscillator was when the wait instruction was executed. the reco very time when multiple oscillators are operati ng is the same period as that when the os cillator, which takes the longest time for recovery among the operating oscillators, is operating alone. figure 6.8 software standby mode cancellation timing table 6.9 timing of recovery from low power consumption modes conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min. typ. max. unit test conditions recovery time after cancellation of software standby mode crystal resonator connected to main clock oscillator main clock oscillator operating t sbymc 10 ? ? ms figure 6.8 main clock oscillator and pll circuit operating t sbypc 10 ? ? ms external clock input to main clock oscillator main clock oscillator operating t sbyex 1??ms main clock oscillator and pll circuit operating t sbype 1??ms low-speed clock oscillator or iwdt-specific low- speed clock oscillator operating t sbylo ? ? 800 s recovery time after cancellation of deep software standby mode t dsby ? ? 1 ms figure 6.9 wait time after cancellation of deep software standby mode t dsbywt 45 ? 46 t cyc oscillator iclk irq software standby mode t sbymc, t sbypc, t sbyex, t sbype, t sbylo
r01ds0087ej0220 rev.2.20 page 159 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] figure 6.9 deep software standby mode cancellation timing 6.3.4 control signal timing note 1. t pcyc : pclk cycle figure 6.10 nmi interrupt input timing figure 6.11 irq interrupt input timing table 6.10 control signal timing conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min. typ. max. unit test conditions nmi pulse width t nmiw 200??nst pcyc 2 200ns, figure 6.10 2t pcyc t pcyc 2 > 200ns, figure 6.10 irq pulse width t irqw 200??nst pcyc 2 200ns, figure 6.11 2t pcyc t pcyc 2 > 200ns, figure 6.11 oscillator irq internal reset reset exception handling start deep software standby mode deep software standby reset t dsby t dsbywt nmi t nmiw irq t irqw
r01ds0087ej0220 rev.2.20 page 160 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] 6.3.5 timing of on-chi p peripheral modules note 1. t pcyc : pclk cycle, t pacye : pclka cycle table 6.11 timing of on-chi p peripheral modules (1) conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min. max. unit* 1 test conditions i/o ports input data pulse width t prw 1.5 ? t pcyc figure 6.12 mtu3 input capture input pulse width single-edge setting t ticw 3?t pacyc figure 6.13 both-edge setting 5? timer clock pulse width single-edge setting t tckwh, t tckwl 3?t pacyc figure 6.14 both-edge setting 5? phase counting mode 5? poe3 poe# input pulse width t poew 1.5 ? t pcyc figure 6.16 gpt input capture input pulse width single-edge setting t gticw 3?t pacyc figure 6.15 both-edge setting 5? external trigger input pulse width single-edge setting t otetw 3?t pacyc figure 6.18 both-edge setting 5? sci input clock cycle asynchronous t scyc 4?t pcyc figure 6.17 clock synchronous 6? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?2 0n s input clock fall time t sckf ?2 0n s output clock cycle asynchronous t scyc 16 ? t pcyc clock synchronous 4? output clock pulse width t sckw 0.4 0.6 t scyc output clock rise time t sckr ?2 0n s output clock fall time t sckf ?2 0n s transmit data delay time clock synchronous t txd ? 40 ns figure 6.18 receive data setup time clock synchronous t rxs 40 ? ns receive data hold time clock synchronous t rxh 40 ? ns a/d converter 12-bit a/d converter trigger input pulse width t trgw 1.5 ? t pcyc figure 6.19
r01ds0087ej0220 rev.2.20 page 161 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] note 1. t pcyc : pclk cycle table 6.12 timing of on-chi p peripheral modules (2) conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min. max. unit* 1 test conditions rspi rspck clock cycle master t spcyc 2 4096 t pcyc figure 6.20 slave 8 4096 rspck clock high pulse width master t spckwh (t spcyc ? t spckr ? t spckf ) / 2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf ) / 2 ? rspck clock low pulse width master t spckwl (t spcyc ? t spckr ? t spckf ) / 2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf ) / 2 ? rspck clock rise/fall time output t spckr, t spckf ?5n s input ? 1 s data input setup time master t su 15 ? ns figure 6.21 to figure 6.24 20 ? slave 20 ? t pcyc ? data input hold time master t h 0?n s slave 20 + 2 t pcyc ? ssl setup time master t lead 18t spcyc slave 4 ? t pcyc ssl hold time master t lag 18t spcyc slave 4 ? t pcyc data output delay time master t od ?1 8n s slave ? 3 t pcyc + 40 data output hold time master t oh 0?n s slave 0 ? successive transmission delay time master t td t spcyc + 2 t pcyc 8 t spcyc + 2 t pcyc ns slave 4 t pcyc ? mosi rise/fall time output t modr, t modf ?5n s input ? 1 s miso rise/fall time output t modr, t modf ?5n s input ? 1 s ssl rise/fall time output t sslr, t sslf ?1 5n s input ? 1 s slave access time t sa ?4t pcyc figure 6.23 and figure 6.24 slave output release time t rel ?3t pcyc
r01ds0087ej0220 rev.2.20 page 162 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] note 1. t pcyc : pclk cycle table 6.13 timing of on-chi p peripheral modules (3) conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min. max. unit* 1 test conditions simple spi sck clock cycle output (master) t spcyc 4 65536 t pcyc figure 6.20 sck clock cycle input (slave) 8 65536 sck clock high pulse width t spckwh 0.4 0.6 t spcyc sck clock low pulse width t spckwl 0.4 0.6 t spcyc sck clock rise/fall time t spckr, t spckf ?2 0n s data input setup time t su 40 ? ns figure 6.21 to figure 6.24 data input hold time t h 40 ? ns ss input setup time t lead 6?t pcyc ss input hold time t lag 6?t pcyc data output delay time t od ?4 0n s data output hold time t oh ?10 ? ns data rise/fall time t dr, t df ?2 0n s ss input rise/fall time t sslr, t sslf ?2 0n s slave access time t sa ?5 t pcyc figure 6.23 and figure 6.24 slave output release time t rel ?5 t pcyc
r01ds0087ej0220 rev.2.20 page 163 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] note 1. t iiccyc : riic internal reference clock (iic ? ) cycle note 2. the value within parentheses is applic able when the value of the icmr3.nf[1:0] bi ts is 11b while the digital filter is e nabled by the setting icfer.nfe = 1. note 3. cb is the total capacitance of the bus lines. table 6.14 timing of on-chi p peripheral modules (4) conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symb ol min. max. unit test conditions riic (standard-mode) scl input cycle time t scl 6(12) t iiccyc + 1300 ? ns figure 6.25 scl input high pulse width t sclh 3(6) t iiccyc + 300 ? ns scl input low pulse width t scll 3(6) t iiccyc + 300 ? ns scl, sda input rise time t sr ? 1000 ns scl, sda input fall time t sf ? 300 ns scl, sda input spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda input bus free time t buf 3(6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns restart condition input setup time t stas 1000 ? ns stop condition input setup time t stos 1000 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf riic (fast-mode) scl input cycle time t scl 6(12) t iiccyc + 600 ? ns scl input high pulse width t sclh 3(6) t iiccyc + 300 ? ns scl input low pulse width t scll 3(6) t iiccyc + 300 ? ns scl, sda input rise time t sr 20 + 0.1c b 300 ns scl, sda input fall time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda input bus free time t buf 3(6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns restart condition input setup time t stas 300 ? ns stop condition input setup time t stos 300 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf
r01ds0087ej0220 rev.2.20 page 164 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] note 1. the value in parentheses is used when icmr3.nf[1:0] are set to 11b while a digital filter is enabled with icfer.nfe = 1. note 2. cb indicates the total capacity of the bus line. figure 6.12 i/o port input timing figure 6.13 mtu3 input/output timing figure 6.14 mtu3 clock input timing table 6.15 timing of on-chi p peripheral modules (5) conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min.* 1, * 2 max. unit test conditions simple iic (standard-mode) scl, sdainput rise time t sr ? 1000 ns figure 6.25 scl, sda input fall time t sf ? 300 ns scl, sda input spike pulse removal time t sp 04 t iiccyc ns data input setup time t sdas 250 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf simple iic (fast-mode) scl, sda input rise time t sr 20 + 0.1c b 300 ns scl, sda input fall time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 04 t iiccyc ns data input setup time t sdas 100 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf port pclk t prw input capture input pclka t ticw mtclka to mtclkd iclk t tckwl t tckwh
r01ds0087ej0220 rev.2.20 page 165 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] figure 6.15 gpt input/output timing figure 6.16 poe3# input timing figure 6.17 sck clock input timing figure 6.18 sci input/output timing: clock synchronous mode input capture input pclka t gticw poen# input pclk t poew t sckw t sckr t sckf t scyc sckn (n = 0, 1, 12) t txd t rxs t rxh txdn rxdn sckn n = 0, 1, 12
r01ds0087ej0220 rev.2.20 page 166 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] figure 6.19 ad converter external trigger input timing figure 6.20 rspi clock timing and simple spi clock timing figure 6.21 rspi timing (master, cpha = 0) and simple spi timing (master, ckph = 1) adtrg0# pclk t trgw rspcka master select output rspcka slave serect input t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 v cc , v ol = 0.3 v cc , v ih = 0.7 v cc , v il = 0.3 v cc t modr , t modf t su t h t lead t td t lag t sslr , t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out ssla3 to ssla0 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output
r01ds0087ej0220 rev.2.20 page 167 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] figure 6.22 rspi timing (master, cpha = 1) and simple spi timing (master, ckph = 0) figure 6.23 rspi timing (slave, cpha = 0) and simple spi timing (slave, ckph = 1) t modr, t modf t su t h t lead t td t lag t sslr , t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od ssla3 to ssla0 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output t sodr, t sodf t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input
r01ds0087ej0220 rev.2.20 page 168 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] figure 6.24 rspi timing (slave, cpha = 1) and simple spi timing (slave, ckph = 0) figure 6.25 riic bus interface input/output timing and simple iic bus interface input/output timing ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input t sodr, t sodf t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out sda scl v ih v il t stah t sclh t scll p * 1 s * 1 t sf t sr t scl t sdah t sdas t stas t sp t stos p * 1 t buf note 1. s, p, and sr indicate the following conditions. s: start condition p: stop condition sr: restart condition test conditions v ih = vcc 0.7, v il = vcc 0.3 v ol = 0.6v, i ol = 6 ma sr * 1
r01ds0087ej0220 rev.2.20 page 169 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] 6.4 a/d conversion characteristics note 1. the conversion time includes the sa mpling time and the comparison time. as t he test conditions, the number of sampling s tates is indicated. table 6.16 12-bit a/d conversion characteristics conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item min typ max unit test conditions resolution 12 12 12 bit conversion time *1 (adclk = 50 mhz) when the sample-and-hold circuit is in use per pin 1.6 ? ? s sampling by the sample-and-hold circuit in 30 states. sampling by the a/d converter in 20 states. when the sample-and-hold circuit is not in use per pin 1.0 ? ? s sampling by the a/d converter in 20 states. analog input capacitance ? ? 6 pf integral nonlinearity error ? ? 4.0 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? 0.5 ? lsb absol ute accur acy sample and hold circuit in use ? ? 8.0 lsb avin = 0.25 to av refh ?0.25 sample and hold circuit not in use ? ? 8.0 lsb avin = av refl to av refh permissible signal source impedance ? ? 3.0 k ? table 6.17 comparator characteristics conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min typ max. unit test conditions analog input capacitance cin ? ? 6 pf refh pin offset voltage voff ? ? 5 mv refl pin offset voltage ? ? 5 mv refh input voltage range vin 1.7 ? avcc ? 0.3 v refl input voltage range 0.3 ? avcc ? 1.7 v refh reply time tcr ? ? 0.5 s refl reply time tcf ? ? 0.5 s
r01ds0087ej0220 rev.2.20 page 170 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] 6.5 power-on reset circuit and voltage detecti on circuit characteristics note 1. the minimum vcc down time indicates the time when vcc is below the minimum value of voltage detection levels v por , v det1, and v det2 for the por/ lvd. figure 6.26 power-on reset timing figure 6.27 voltage detection circuit timing (v det0 ) table 6.18 power-on reset circuit and voltage detection circuit characteristics conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) v por 2.5 2.6 2.7 v figure 6.26 voltage detection circuit (lvd0) v det0 2.7 2.8 2.9 figure 6.27 voltage detection circuit (lvd1) v det1 2.80 2.95 3.10 voltage detection circuit (lvd2) v det2 2.80 2.95 3.10 internal reset time power-on reset (por) t por ? 4.6 ms figure 6.26 voltage detection circuit (lvd0) t lvd0 ? 4.6 figure 6.27 voltage detection circuit (lvd1) t lvd1 ? 0.9 figure 6.28 voltage detection circuit (lvd2) t lvd2 ? 0.9 figure 6.29 minimum vcc down time* 1 t voff 200 ? ? s figure 6.26, figure 6.27 response delay time t det 200 s figure 6.26 to figure 6.29 lvd operation stabilization time (after lvd is enabled) td (e-a) 3 s figure 6.28 figure 6.29 hysteresis width (lvd1 and lvd2) v lvh 80 mv internal reset signal (active-low) vcc t voff t det t por t det t por t det v por t voff t lvd0 t det v det0 vcc internal reset signal (active-low)
r01ds0087ej0220 rev.2.20 page 171 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] figure 6.28 voltage detection circuit timing (v det1 ) figure 6.29 voltage detection circuit timing (v det2 ) t voff v det1 vcc t det t det t lvd1 t d(e-a) lvd1e lvd1 comparator output lvd1cmpe lvd1mon internal reset signal (active-low) when lvd1rn = l when lvd1rn = h v lvh t lvd1 t voff v det2 vcc t det t det t lvd2 t d(e-a) lvd2e lvd2 comparator output lvd2cmpe lvd2mon internal reset signal (active-low) when lvd2rn = l when lvd2rn = h v lvh t lvd2
r01ds0087ej0220 rev.2.20 page 172 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] 6.6 oscillation stop detecti on circuit characteristics figure 6.30 oscillation stop detection timing table 6.19 oscillation stop detection circuit characteristics conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min. typ. max. unit test conditions detection time t dr ? ? 1.0 ms figure 6.30 t dr main clock ostdsr.ostdf low-speed clock iclk
r01ds0087ej0220 rev.2.20 page 173 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] 6.7 rom (flash memory for code storage) characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 1000), erasing can be performed n times for each block. for instance, when 128-byte programming is performed 16 times for different addresses in 2-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (ove rwriting is prohibited). note 2. the value is obtained from the reliability test. table 6.20 rom (flash memory for code storage) characteristics (1) condition: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, temperature range for the programming/erasure operation: t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions reprogram/erase cycle* 1 n pec 1000 ? ? times data hold time t drp 30* 2 ? ? year ta = +85c table 6.21 rom (flash memory for code storage) characteristics (2) conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, temperature range for the programming/erasure operation: t a = t opr . t a is common to conditions 1 to 3. item symbol min typ max unit test conditions programming time 128 bytes t p128 ? 1 10 ms fclk = 50mhz n pec 100 4 kbytes t p4k ?2 35 0m s 16 kbytes t p16k ? 90 200 ms 128 bytes t p128 ? 1.2 12 ms fclk=50mhz n pec > 100 4 kbytes t p4k ? 27.6 60 ms 16 kbytes t p16k ? 108 240 ms erasure time 4 kbytes t e4k ? 25 60 ms fclk=50mhz n pec 100 16 kbytes t e16k ? 100 240 ms 4 kbytes t e4k ? 30 72 ms fclk=50mhz n pec > 100 16 kbytes t e16k ? 120 288 ms suspend delay time during programming t spd ? ? 120 s figure 6.31 fclk = 50mhz first suspend delay time during erasing (in suspend priority mode) t sesd1 ? ? 120 s second suspend delay time during erasing (in suspend priority mode) t sesd2 ??1 . 7m s suspend delay time during erasing (in erasure priority mode) t seed ??1 . 7m s fcu reset time t fcur 35 ? ? s
r01ds0087ej0220 rev.2.20 page 174 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] 6.8 e 2 dataflash characteristic note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 1000), erasing can be performed n times for each block. for instance, when 128-byte programming is performed 16 times for different addresses in 2-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (ove rwriting is prohibited). note 2. the value is obtained from the reliability test. table 6.22 e 2 dataflash (flash memory for data storage) characteristics (1) conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0 temperature range for the programming/erasure operation: t a = t opr . t a is common to conditions 1 to 3. item symbol min. typ. max. unit test conditions reprogram/erase cycle* 1 n dpec 100000 ? ? times data hold time t ddrp 30* 2 ? ? year ta = +85c table 6.23 e 2 dataflash (flash memory for data storage) characteristics (2) conditions: vcc = 2.7 to 3.6 v, vss = avss0 = vrefl0 = 0 v, avcc0 = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, ta = t opr item symbol min typ max unit test condition programming time 2 bytes t dp2 ? 0.25 2 ms fclk = 50 mhz erasure time 32 bytes t de32 ? 2 20 ms fclk = 50 mhz n dpec 100 32 bytes t de32 ? 4 20 ms fclk = 50 mhz n dpec > 100 blank check time 2 bytes t dbc2 ??3 0 s fclk = 50 mhz suspend delay time during programming t dspd ? ? 120 s figure 6.31 pclkb = 50 mhz first suspend delay time during erasing (in suspend priority mode) t dsesd1 ? ? 120 s second suspend delay time during erasing (in suspend priority mode) t dsesd2 ? ? 300 s suspend delay time during erasing (in erasure priority mode) t dseed ? ? 300 s
r01ds0087ej0220 rev.2.20 page 175 of 186 mar 31, 2016 rx63t group 6. electrical characte ristics [64- and 48-pin versions] figure 6.31 flash memory pr ogram/erase suspend timing fcu command fstatr0.frdy programming pulse ? suspension during programming fcu command fstatr0.frdy erasure pulse ? suspension during erasure in suspend priority mode fcu command fstatr0.frdy erasure pulse ? suspension during erasure in erasure priority mode program suspend ready not ready ready programming t spd erase suspend ready not ready ready t seed erasing erase suspend resume suspend ready not ready ready not ready t sesd1 t sesd2 erasing erasing
r01ds0087ej0220 rev.2.20 page 176 of 186 mar 31, 2016 rx63t group appendix 1. package dimensions appendix 1. pa ckage dimensions information on the latest version of the package dimensions or mountings has been displayed in ?packages? on renesas electronics corporation website. figure a 144-pin lqfp (plqp0144ka-a) terminal cross section b 1 c 1 b p c 1.0 0.125 0.20 1.25 1.25 0.08 0.20 0.145 0.09 0.27 0.220.17 max nom min dimension in millimeters symbol reference 20.1 20.019.9 d 20.1 20.019.9 e 1.4 a 2 22.222.0 21.8 22.222.0 21.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 p-lqfp144-20x20-0.50 1.2g mass[typ.] 144p6q-a / fp-144l / fp-144lv plqp0144ka-a renesas code jeita package code previous code f 1 36 37 72 73 108 109 144 *1 *2 *3 x index mark h e e d h d b p z d z e detail f c a l a 1 a 2 l 1 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. e y s s
r01ds0087ej0220 rev.2.20 page 177 of 186 mar 31, 2016 rx63t group appendix 1. package dimensions figure b 120-pin lqfp (plqp0120ka-a) terminal cross section c detail f c l a s s e d *2 *3 *1 f 120 91 90 61 60 31 30 index mark y e 1 include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. previous code jeita package code renesas code plqp0120ka-a ? mass[typ.] 0.9g p-lqfp120-16x16-0.50 l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 17.8 18.0 18.2 17.8 18.0 18.2 a 2 1.4 e 15.9 16.0 16.1 d 15.9 16.0 16.1 reference symbol dimension in millimeters min nom max 0.17 0.22 0.27 0.09 0.145 0.20 0.08 0.75 0.75 0.20 0.125 1.0 z e b p z d h e b p b 1 c 1 h d m a 2 a 1 l 1
r01ds0087ej0220 rev.2.20 page 178 of 186 mar 31, 2016 rx63t group appendix 1. package dimensions figure c 112-pin lqfp (plqp0112ja-a) detail f a l c terminal cross section b p c 1 b 1 c s s e y index mark 1 28 29 56 57 84 85 112 f *3 *1 *2 e z d z e h d d h e b p 2. 1. dimensions " *1" and " *2" do not include mold flash. note) dimension " *3" does not include trim offset. l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.10 e 8 0 0.65 c x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 21.8 22.0 22.2 21.8 22.0 22.2 a 2 1.4 e 19.9 20.0 20.1 d 19.9 20.0 20.1 reference symbol dimension in millimeters min nom max 0.27 0.32 0.37 0.09 0.145 0.20 0.13 1.225 1.225 0.30 0.125 1.0 p-lqfp112-20x20-0.65 1.2g mass[typ.] fp-112e/fp-112ev plqp0112ja-a renesas code jeita package code previous code m a 1 a 2 l 1
r01ds0087ej0220 rev.2.20 page 179 of 186 mar 31, 2016 rx63t group appendix 1. package dimensions figure d 100-pin lqfp (plqp0100kb-a) terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. index mark x 12 5 26 50 51 75 76 100 f *1 *3 *2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e y s s
r01ds0087ej0220 rev.2.20 page 180 of 186 mar 31, 2016 rx63t group appendix 1. package dimensions figure e 64-pin lqfp (plqp0064kb-a) terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and " *2" do not include mold flash. note) dimension "*3" does not include trim offset. index mark *3 17 32 64 49 116 33 48 f *1 *2 x b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nommin dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.011.8 12.2 12.011.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e y s s
r01ds0087ej0220 rev.2.20 page 181 of 186 mar 31, 2016 rx63t group appendix 1. package dimensions figure f 48-pin lqfp (PLQP0048KB-A) terminal cross section b 1 c 1 bp c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension " *3" does not include trim offset. detail f l 1 c a l a 1 a 2 *3 f 48 37 36 25 24 13 12 1 *1 *2 x index mark z e z d b p e h e h d d e previous code jeita package code renesas code PLQP0048KB-A 48p6q-a mass[typ.] 0.2g p-lqfp48-7x7-0.50 1.0 0.125 0.20 0.75 0.75 0.08 0.20 0.145 0.09 0.270.22 0.17 maxnommin dimension in millimeters symbol reference 7.17.06.9 d 7.17.06.9 e 1.4 a 2 9.2 9.08.8 9.2 9.08.8 1.7 a 0.2 0.1 0 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s
r01ds0087ej0220 rev.2.20 page 182 of 186 mar 31, 2016 rx63t group revision history revision history rx 63t group datasheet rev. date description page summary 1.00 aug 28, 2012 ? first edition issued 2.00 mar 11, 2013 features 1 changed 1. overview 2 1.1 outline of specif ications, description changed 2 to 8 table 1.1 outline of specifications, changed 9 table 1.2 comparison of functions for different packages, changed 10 to 12 table 1.3 list of products, changed 12 figure 1.1 how to read the product part number, changed 13 figure 1.2 block diagram, changed 14 to 18 table 1.4 pin functions, changed 19 figure 1.3 pin assignment (144-pin lqfp), added 20 figure 1.4 pin assignment (120-pin lqfp), added 21 figure 1.5 pin assignment (112-pin lqfp), added 22 figure 1.6 pin assignment (100-pin lqfp), added 23 figure 1.7 pin assignment (64-pin lqfp), notes changed 24 figure 1.8 pin assignment (48-pin lqfp), notes changed 25 to 28 table 1.5 list of pins and pin functions (144-pin lqfp), added 29 to 32 table 1.6 list of pins and pin functions (120-pin lqfp), added 33 to 36 table 1.7 list of pins and pin functions (112-pin lqfp), added 37 to 39 table 1.8 list of pins and pin functions (100-pin lqfp), added 3. address space 49 figure 3.1 memory map in each operating mode, changed 50 3.2 external address space, added 4. i/o registers 52 (3) number of access cycles to i/o registers, description changed 53 to 103 table 4.1 list of i/o registers (address order), changed 5. electrical characteristics [1 44-, 120-, 112- and 100-pin versions] 104 to 148 added 6. electrical characterist ics [64- and 48-pin versions] 149 title changed 152 table 6.6 clock timing, changed 158 table 6.10 timing of on-chip peripheral modules (1), changed 160 table 6.12 timing of on-chip peripheral modules (3), changed 170 6.6 oscillation stop detection ci rcuit characterist ics, title changed 170 table 6.18 oscillation stop detection circuit characteristics, title changed 171 table 6.19 rom (flash memory for code storage) characteristics (1), added 171 table 6.20 rom (flash memory for code stor age) characteristics (2), title and description changed 172 table 6.21 dataflash (flash memory for data storage) characteristics (1), added 172 table 6.22 dataflash (flash memory for data st orage) characteristics (2), title and description changed appendix 1. package dimensions 174 to 177 figure a 144-pin lqfp (plqp0144ka-a) to figure d 100-pin lqfp (plqp0100kb-a), added 2.10 sep 26, 2013 the rx63t group and rx63t changed to this mcu features 1 changed 1. overview 2 to 8 table 1.1 outline of specifications, changed, note 1, added. 9 table 1.2 comparison of functions for different packages, changed, note 2, added. 10 to 14 table 1.3 list of products, changed, note 1, added 15 figure 1.1 how to read the product part number, changed 28 to 31 table 1.5 list of pins and pin functions (144-pin lqfp), changed 32 to 35 table 1.6 list of pins and pin functions (120-pin lqfp), changed revision history
r01ds0087ej0220 rev.2.20 page 183 of 186 mar 31, 2016 rx63t group revision history 2.10 sep 26, 2013 36 to 39 table 1.7 list of pins and pin functions (112-pin lqfp), changed 40 to 42 table 1.8 list of pins and pin functions (100-pin lqfp), changed 43 to 45 table 1.9 list of pins and pin functions (64-pin lqfp), changed 46 to 47 table 1.10 list of pins and pin functions (48-pin lqfp), changed 4. i/o registers 56 to 103 table 4.1 list of i/o registers (address order), changed 5. electrical characteristics [1 44-, 120-, 112- and 100-pin versions] 104 table 5.1 absolute maximum ratings, changed 107 table 5.4 dc characteristics (3), note 7, deleted 108 table 5.6 permissible power consumption, added 128 5.3.7 timing of pwm delay generation circuit, added 128 table 42.21 timing of the pw m delay generation circuit, added 132 figure 5.32 rspi timing (master, cpha = 1) (bit rate: pclkb division ratio set to a value other than 1/2) and simple spi timing (master, ckph = 1), changed 133 figure 5.34 rspi timing (slave, cpha = 0) and simple spi timing (slave, ckph = 0), changed 134 figure 5.35 rspi timing (slave, cpha = 1) and simple spi timing (slave, ckph = 1), changed 6. electrical characterist ics [64- and 48-pin versions] 149 table 6.1 absolute maximum ratings, changed 151 table 6.3 dc characteristics (2), note 3, changed 152 table 6.5 permissible power consumption, added rev. date description page summary
r01ds0087ej0220 rev.2.20 page 184 of 186 mar 31, 2016 rx63t group revision history classifications - items with technical update document number: changes according to the corresponding i ssued technical update - items without technical update documen t number: minor changes that do not re quire technical update to be issued rev. date description classification page summary 2.20 mar 31, 2016 1. overview 2 to 8 table 1.1 outline of specif ications, note 1 changed tn-rx*-a086a/e 10 to 13 table 1.3 list of products, changed tn-rx*-a086a/e 16 table 1.4 pin functions, changed 27 to 30 table 1.5 list of pins an d pin functions (144-pin lqfp), changed 30 table 1.5 list of pins and pin functions (144-pin lqfp), note 1 added 31 to 34 table 1.6 list of pins an d pin functions (120-pin lqfp), changed 35 to 38 table 1.7 list of pins and pin functions (112-pin lqfp), changed 38 table 1.7 list of pins and pin functions (112-pin lqfp), note 1 added 4. i/o registers 54 (4) notes on sleep mode and mode transition, added tn-rx*-a140a/e 55 to 102 table 4.1 list of i/o registers (address order), changed tn-rx*-a086a/e, tn-rx*-a140a/e 5. electrical characteristics [144-, 120-, 112- and 100-pin versions] 103 table 5.1 absolute maximum ratings, changed tn-rx*-a086a/e 106 table 5.4 dc characteristics (3), changed 107 table 5.5 permissible output currents, changed 108 table 5.6 permissible power consumpti on (g version product only), title changed, notes added tn-rx*-a086a/e 111 table 5.9 clock timing, changed tn-rx*-a097a/e 112 figure 5.6 loco, iwdtclk clock oscillation start timi ng, title changed tn-rx*-a097a/e 112 figure 5.6 loco, iwdtclk clock osci llation start timing, changed tn-rx*-a097a/e 124 table 5.16 timing of on-chip peripheral modules (1), changed tn-rx*-a121a/e 125 table 5.16 timing of on-chip peripheral modules (2), changed tn-rx*-a121a/e 126 table 5.16 timing of on-chip peripheral modules (3), changed tn-rx*-a121a/e 127 table 5.16 timing of on-chip peripheral modules (4), changed 129 table 5.17 timing of the pwm de lay generation circuit tn-rx*-a086a/e 132 figure 5.30 rspi timing (master, cpha = 0) (bit rate: pclkb division ratio set to a value other than 1/2) and simple spi timing (master, ckph = 1), title and figure changed 133 figure 5.32 rspi timing (master, cpha = 1) (bit rate: pclkb division ratio set to a value other than 1/2) and simple spi timing (master, ckph = 0), title changed 134 figure 5.34 rspi timing (slave, cpha = 0) and simple spi timing (slave, ckph = 1), title changed 135 figure 5.35 rspi timing (slave, cpha = 1) and simple spi timing (slave, ckph = 0), title changed 136 table 5.18 on-chip usb full-speed characteristics (dp and dm pin characteris- tics), condition 1, 2 changed tn-rx*-a086a/e 143 table 5.26 power-on reset circuit and vo ltage detection circuit characteristics (1), changed 6. electrical characteristic s [64- and 48-pin versions] 150 table 6.1 absolute maximum ratings, changed tn-rx*-a086a/e 153 table 6.5 permissible power consumpti on (g version product only), title changed, note added tn-rx*-a086a/e 154 table 6.7 clock timing, changed tn-rx*-a097a/e 155 figure 6.3 loco, iwdtclk clock oscillation start timi ng, title changed tn-rx*-a097a/e 155 figure 6.3 loco, iwdtclk clock osci llation start timing, changed tn-rx*-a097a/e 161 table 6.12 timing of on-chip peripheral modules (2), changed 170 table 6.18 power-on reset circuit and volt age detection circuit characteristics, changed
general precautions in the handling of microprocessing unit and microcontroller unit products the following usage notes are applicable to all microprocessing unit and microcontroller unit products from renesas. for detailed usage notes on the products cov ered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accordance with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high - impedance state. in operation with an unused pin in the open - circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot - through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power - on the state of the prod uct is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on - chip power - on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ? the characteristics of microprocessing unit or microcontroller unit products in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system - evaluation test for the given product.
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